Patents by Inventor Keishiro Amaya
Keishiro Amaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190311842Abstract: A coil component including an element assembly that contains a filler and a resin material, a coil portion composed of a coil conductor that is embedded in the element assembly, and a pair of outer electrodes electrically connected to the coil conductor. Also, the coil conductor is covered with a glass layer.Type: ApplicationFiled: April 2, 2019Publication date: October 10, 2019Applicant: Murata Manufacturing Co., Ltd.Inventors: Katsuhisa IMADA, Keiichi YOSHINAKA, Keishiro AMAYA, Hiroyuki KANBARA
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Patent number: 8975996Abstract: Provided is an electronic component that can suppress the occurrence of disconnections between line conductor layers and via hole conductors and a method of manufacturing the electronic component. A multilayer body is formed by stacking insulating layers. A conductor layer is provided on a first insulating layer. A line conductor layer is provided on a second insulating layer that is provided on an upper side of the first insulating layer in a stacking (z-axis) direction. A via hole conductor connects an end portion of the line conductor layer to the conductor layer and extends through the second insulating layer in the z-axis direction. In the via hole conductor, a connection surface connected to the line conductor layer is formed of a circular portion and a protrusion. The protrusion protrudes from the circular portion in the x-axis direction in which the line conductor layer extends from the end portion.Type: GrantFiled: February 13, 2013Date of Patent: March 10, 2015Assignee: Murata Manufacturing Co., Ltd.Inventors: Satoki Sakai, Keishiro Amaya, Eita Tamezawa
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Patent number: 7160770Abstract: A small size electronic component has a small direct current resistance value of a conductor pattern and minimal dimensional irregularity of a conductor pattern. In order to form such a component, a photosensitive conductive paste applied on a ceramic substrate and is then exposed through a photo mask and developed so as to form a lower conductor pattern layer of a coil conductor pattern. Then an insulating paste is applied on the ceramic substrate so as to cover the lower conductor pattern layer and the insulating paste is removed with a solvent until at least the upper surface of the lower conductor pattern layer is exposed so as to form an inter-line insulating layer. Furthermore, after applying a photosensitive conductive paste as a film, the exposure and development operation is conducted again while using the photo mask so as to form an upper conductor pattern layer on the lower conductor pattern layer.Type: GrantFiled: October 12, 2002Date of Patent: January 9, 2007Assignee: Murata Manufacturing Co., Ltd.Inventors: Toshiya Sasaki, Kazuyoshi Uchiyama, Masahiko Kawaguchi, Keishiro Amaya, Eita Tamezawa
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Patent number: 6723494Abstract: A conductor pattern is constructed to prevent corners from peeling and raising off a substrate. The conductor pattern has a spiral configuration and includes straight lines and corners connected to the straight lines. The bottom surface cross-sectional width of the conductor pattern is smaller than the top surface cross-sectional width thereof. Moreover, the bottom surface cross-sectional width of the corner is larger than the bottom surface cross-sectional width of the straight line.Type: GrantFiled: July 12, 2001Date of Patent: April 20, 2004Assignee: Murata Manufacturing Co., Ltd.Inventors: Yasuhiro Nakata, Keishiro Amaya
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Patent number: 6686825Abstract: A chip inductor has electrode layers, insulating layers disposed on the electrode layers, and an uppermost insulating layer all disposed on a ceramic board. An inorganic pigment such as a Co oxide or an Al oxide is added to the insulating layer at a concentration of from about 2% to about 20% by weight. Break grooves are formed in the form of a lattice on the insulating layer by a laser beam irradiation, and the board is divided along the grooves. By adding the inorganic pigment, the break grooves are effectively formed, and the mother board is divided accurately along the break grooves, such that a chip inductor having an increased L value and an increased Q value is produced.Type: GrantFiled: November 8, 2002Date of Patent: February 3, 2004Assignee: Murata Manufacturing Co., Ltd.Inventors: Eita Tamezawa, Keishiro Amaya
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Publication number: 20030095028Abstract: A chip inductor has electrode layers, insulating layers disposed on the electrode layers, and an uppermost insulating layer all disposed on a ceramic board. An inorganic pigment such as a Co oxide or an Al oxide is added to the insulating layer at a concentration of from about 2% to about 20% by weight. Break grooves are formed in the form of a lattice on the insulating layer by a laser beam irradiation, and the board is divided along the grooves. By adding the inorganic pigment, the break grooves are effectively formed, and the mother board is divided accurately along the break grooves, such that a chip inductor having an increased L value and an increased Q value is produced.Type: ApplicationFiled: November 8, 2002Publication date: May 22, 2003Applicant: Murata Manufacturing Co., Ltd.Inventors: Eita Tamezawa, Keishiro Amaya
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Patent number: 6555913Abstract: A small size electronic component has a small direct current resistance value of conductor pattern and minimal dimensional irregularity of a conductor pattern. In order to form such a component, a photosensitive conductive paste applied on a ceramic substrate and is then exposed through a photo mask and developed so as to form a lower conductor pattern layer of a coil conductor pattern. Then an insulating paste is applied on the ceramic substrate so as to cover the lower conductor pattern layer and the insulating paste is removed with a solvent until at least the upper surface of the lower conductor pattern layer is exposed so as to form an inter-line insulating layer. Furthermore, after applying a photosensitive conductive paste as a film, the exposure and development operation is conducted again while using the photo mask so as to form an upper conductor pattern layer on the lower conductor pattern layer.Type: GrantFiled: July 8, 1999Date of Patent: April 29, 2003Assignee: Murata Manufacturing Co., Ltd.Inventors: Toshiya Sasaki, Kazuyoshi Uchiyama, Masahiko Kawaguchi, Keishiro Amaya, Eita Tamezawa
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Patent number: 6538547Abstract: A chip inductor has electrode layers, insulating layers disposed on the electrode layers, and an uppermost insulating layer all disposed on a ceramic board. An inorganic pigment such as a Co oxide or an Al oxide is added to the insulating layer at a concentration of from about 2% to about 20% by weight. Break grooves are formed in the form of a lattice on the insulating layer by a laser beam irradiation, and the board is divided along the grooves. By adding the inorganic pigment, the break grooves are effectively formed, and the mother board is divided accurately along the break grooves, such that a chip inductor having an increased L value and an increased Q value is produced.Type: GrantFiled: May 9, 2001Date of Patent: March 25, 2003Assignee: Murata Manufactruing Co., Ltd.Inventors: Eita Tamezawa, Keishiro Amaya
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Publication number: 20030038372Abstract: A small size electronic component has a small direct current resistance value of a conductor pattern and minimal dimensional irregularity of a conductor pattern. In order to form such a component, a photosensitive conductive paste applied on a ceramic substrate and is then exposed through a photo mask and developed so as to form a lower conductor pattern layer of a coil conductor pattern. Then an insulating paste is applied on the ceramic substrate so as to cover the lower conductor pattern layer and the insulating paste is removed with a solvent until at least the upper surface of the lower conductor pattern layer is exposed so as to form an inter-line insulating layer. Furthermore, after applying a photosensitive conductive paste as a film, the exposure and development operation is conducted again while using the photo mask so as to form an upper conductor pattern layer on the lower conductor pattern layer.Type: ApplicationFiled: October 12, 2002Publication date: February 27, 2003Applicant: Murata Manufacturing Co., Ltd.Inventors: Toshiya Sasaki, Kazuyoshi Uchiyama, Masahiko Kawaguchi, Keishiro Amaya, Eita Tamezawa
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Publication number: 20020167387Abstract: A chip inductor has electrode layers, insulating layers disposed on the electrode layers, and an uppermost insulating layer all disposed on a ceramic board. An inorganic pigment such as a Co oxide or an Al oxide is added to the insulating layer at a concentration of from about 2% to about 20% by weight. Break grooves are formed in the form of a lattice on the insulating layer by a laser beam irradiation, and the board is divided along the grooves. By adding the inorganic pigment, the break grooves are effectively formed, and the mother board is divided accurately along the break grooves, such that a chip inductor having an increased L value and an increased Q value is produced.Type: ApplicationFiled: May 9, 2001Publication date: November 14, 2002Inventors: Eita Tamezawa, Keishiro Amaya
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Publication number: 20020048630Abstract: A conductor pattern is constructed to prevent corners from peeling and raising off a substrate. The conductor pattern has a spiral configuration and includes straight lines and corners connected to the straight lines. The bottom surface cross-sectional width of the conductor pattern is smaller than the top surface cross-sectional width thereof. Moreover, the bottom surface cross-sectional width of the corner is larger than the bottom surface cross-sectional width of the straight line.Type: ApplicationFiled: July 12, 2001Publication date: April 25, 2002Applicant: Murata Manufacturing Co., LtdInventors: Yasuhiro Nakata, Keishiro Amaya
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Patent number: 6194248Abstract: The present invention is a chip electronic part having: a ceramic member; a conductor pattern formed on the surface of the ceramic member; an insulating protective layer formed on the conductor pattern; an external electrode which is formed at least one end face of the ceramic member, electrically connected to the conductor pattern, and composed of an undercoating layer formed by dry plating and at least one plating layer formed by wet plating; and at least one groove formed near an end face of the insulating protective layer so as to limit the formation of the undercoating layer.Type: GrantFiled: August 5, 1999Date of Patent: February 27, 2001Assignee: Murata Manufacturing Co., Ltd.Inventors: Keishiro Amaya, Kenichi Aoki
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Patent number: 5973390Abstract: The present invention is a chip electronic part having: a ceramic member; a conductor pattern formed on the surface of the ceramic member; an insulating protective layer formed on the conductor pattern; an external electrode which is formed at least one end face of the ceramic member, electrically connected to the conductor pattern, and composed of an undercoating layer formed by dry plating and at least one plating layer formed by wet plating; and at least one groove formed near an end face of the insulating protective layer so as to limit the formation of the undercoating layer.Type: GrantFiled: September 2, 1997Date of Patent: October 26, 1999Assignee: Murata Manufacturing Co., Ltd.Inventors: Keishiro Amaya, Kenichi Aoki