Patents by Inventor Keishiro Okamoto
Keishiro Okamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9462693Abstract: An electronic device includes: a first electronic component; first members that are provided on a first surface of the first electronic component and that include outside surfaces configured to face diagonally upward with respect to the first surface; a second electronic component provided above the first surface; second members that are provided corresponding to the first members on a second surface of the second electronic component which faces the first surface and that include inside surfaces configured to face diagonally downward with respect to the second surface and configured to face the outside surfaces; and solder that is provided between the first surface and the second surface and that electrically connects the first electronic component and the second electronic component.Type: GrantFiled: August 8, 2014Date of Patent: October 4, 2016Assignee: FUJITSU LIMITEDInventors: Keishiro Okamoto, Seiki Sakuyama
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Patent number: 9177938Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.Type: GrantFiled: August 7, 2014Date of Patent: November 3, 2015Assignee: FUJITSU LIMITEDInventors: Motoaki Tani, Keishiro Okamoto
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Patent number: 9082756Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.Type: GrantFiled: March 26, 2014Date of Patent: July 14, 2015Assignee: Fujitsu LimitedInventors: Kozo Shimizu, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe
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Publication number: 20150171053Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.Type: ApplicationFiled: August 7, 2014Publication date: June 18, 2015Applicant: FUJITSU LIMITEDInventors: Motoaki TANI, Keishiro OKAMOTO
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Publication number: 20150132865Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.Type: ApplicationFiled: January 20, 2015Publication date: May 14, 2015Applicant: FUJITSU LIMITEDInventors: Masataka Mizukoshi, Yoshiharu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
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Patent number: 8962470Abstract: A semiconductor substrate is secured by suction to a rear face of a supporting face of a substrate supporting table. In this event, the thickness of the semiconductor substrate is made fixed by planarization on the rear face, and the rear face is forcibly brought into a state free from undulation by the suction to the supporting face, so that the rear face becomes a reference face for planarization of a front face. In this state, a tool is used to cut surface layers of Au projections and a resist mask on the front face, thereby planarizing the Au projections and the resist mask so that their surfaces become continuously flat. This can planarize the surfaces of fine bumps formed on the substrate at a low cost and a high speed in place of CMP.Type: GrantFiled: March 30, 2009Date of Patent: February 24, 2015Assignee: Fujitsu LimitedInventors: Masataka Mizukoshi, Yoshikatsu Ishizuki, Kanae Nakagawa, Keishiro Okamoto, Kazuo Teshirogi, Taiji Sakai
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Publication number: 20150049450Abstract: An electronic device includes: a first electronic component; first members that are provided on a first surface of the first electronic component and that include outside surfaces configured to face diagonally upward with respect to the first surface; a second electronic component provided above the first surface; second members that are provided corresponding to the first members on a second surface of the second electronic component which faces the first surface and that include inside surfaces configured to face diagonally downward with respect to the second surface and configured to face the outside surfaces; and solder that is provided between the first surface and the second surface and that electrically connects the first electronic component and the second electronic component.Type: ApplicationFiled: August 8, 2014Publication date: February 19, 2015Applicant: FUJITSU LIMITEDInventors: Keishiro Okamoto, Seiki Sakuyama
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Patent number: 8866312Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.Type: GrantFiled: January 26, 2012Date of Patent: October 21, 2014Assignee: Fujitsu LimitedInventors: Motoaki Tani, Keishiro Okamoto
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Publication number: 20140203444Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.Type: ApplicationFiled: March 26, 2014Publication date: July 24, 2014Applicant: FUJITSU LIMITEDInventors: KOZO SHIMIZU, KEISHIRO OKAMOTO, NOBUHIRO IMAIZUMI, TADAHIRO IMADA, KEIJI WATANABE
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Patent number: 8728867Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.Type: GrantFiled: January 23, 2012Date of Patent: May 20, 2014Assignee: Fujitsu LimitedInventors: Kozo Shimizu, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe
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Patent number: 8674520Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.Type: GrantFiled: January 23, 2012Date of Patent: March 18, 2014Assignee: Fujitsu LimitedInventors: Nobuhiro Imaizumi, Keishiro Okamoto, Keiji Watanabe
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Patent number: 8492784Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.Type: GrantFiled: December 20, 2011Date of Patent: July 23, 2013Assignee: Fujitsu LimitedInventors: Keishiro Okamoto, Tadahiro Imada, Nobuhiro Imaizumi, Keiji Watanabe
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Patent number: 8257542Abstract: A stack of 50 layers of a first pitch-base carbon fiber sheet is formed, two sets of stack each having two second pitch-base carbon fiber sheets stacked therein are fabricated. At this time, the second carbon fiber sheets have a thermal expansion coefficient larger than that of the first carbon fiber sheet. Next, the stack of the first carbon fiber sheet is then held between two sets of stack of the second carbon fiber sheets. The stack of the first and second carbon fiber sheets are then impregnated with an epoxy-base resin composition and the resin is solidified. As a result a prepreg composed of the first and second carbon fiber sheets and the resin component composed of the epoxy-base resin composition is obtained. Thereafter, interconnections and the like are then formed on the prepreg, to thereby complete a multilevel interconnection board.Type: GrantFiled: October 9, 2009Date of Patent: September 4, 2012Assignee: Fujitsu LimitedInventors: Keishiro Okamoto, Mamoru Kurashina, Tomoyuki Abe
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Publication number: 20120217626Abstract: A method for manufacturing a semiconductor device, includes: placing a seal layer including a connection conductive film on the surface so that the connection conductive film is in contact with an electrode of a semiconductor element and a lead; electrically coupling the electrode and the lead through the connection conductive film; and sealing the semiconductor element by the seal layer.Type: ApplicationFiled: January 19, 2012Publication date: August 30, 2012Applicant: FUJITSU LIMITEDInventors: Taiji SAKAI, Kazukiyo Joshin, Tadahiro Imada, Nobuhiro Imaizumi, Keishiro Okamoto
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Publication number: 20120217660Abstract: A semiconductor apparatus includes: a semiconductor device including a first electrode; a substrate including a second electrode and a recess; and a heat-dissipating adhesive material to set the semiconductor device in the recess so as to arrange the first electrode close to the second electrode, wherein the first electrode is coupled to the second electrode and the heat-dissipating adhesive material covers a bottom surface and at least part of a side surface of the semiconductor device.Type: ApplicationFiled: January 26, 2012Publication date: August 30, 2012Applicant: FUJITSU LIMITEDInventors: Motoaki TANI, Keishiro Okamoto
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Publication number: 20120211764Abstract: A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.Type: ApplicationFiled: January 27, 2012Publication date: August 23, 2012Applicant: FUJITSU LIMITED,Inventors: Keishiro OKAMOTO, Tadahiro IMADA, Nobuhiro IMAIZUMI, Keiji WATANABE
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Publication number: 20120211899Abstract: A method for manufacturing a semiconductor device includes placing a sheet containing a fibrous material having at least one outer surface having a metal on a semiconductor chip-mounting region of a substrate; forming a bonding layer containing a fusible metal on the semiconductor chip-mounting region; placing a semiconductor chip on the semiconductor chip-mounting region; and bonding the semiconductor chip to the semiconductor chip-mounting region with the fusible metal-containing bonding layer by heating.Type: ApplicationFiled: January 23, 2012Publication date: August 23, 2012Applicant: FUJITSU LIMITEDInventors: Nobuhiro IMAIZUMI, Keishiro Okamoto, Keiji Watanabe
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Publication number: 20120211762Abstract: A semiconductor device includes: a semiconductor chip having an electrode; a lead corresponding to the electrode; a metal line coupling the electrode to the lead; a first resin portion covering a coupling portion between the metal line and the electrode and a coupling portion between the metal line and the lead; and a second resin portion covering the metal line, the first resin portion, and the semiconductor chip.Type: ApplicationFiled: December 22, 2011Publication date: August 23, 2012Applicant: FUJITSU LIMITEDInventors: Tadahiro IMADA, Keishiro Okamoto, Nobuhiro Imaizumi, Toshihide Kikkawa
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Publication number: 20120211901Abstract: A manufacturing of a semiconductor device includes forming one of a layer with a first metal and the layer with a second metal on one of a semiconductor chip mounting area of a support plate and a back surface of the semiconductor chip; forming the other of the layer with the first metal and the layer with the second metal on an area corresponding to a part of the area, in which one of the layer with the first metal and the layer with the second metal, of the other one of the semiconductor chip mounting area and the back surface of the semiconductor chip; and forming a layer which includes an alloy with the first metal and the second metal after positioning the semiconductor chip in the semiconductor chip mounting area to bond the semiconductor chip with the semiconductor chip mounting area.Type: ApplicationFiled: January 23, 2012Publication date: August 23, 2012Applicant: FUJITSU LIMITEDInventors: Kozo SHIMIZU, Keishiro Okamoto, Nobuhiro Imaizumi, Tadahiro Imada, Keiji Watanabe
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Publication number: 20120199991Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.Type: ApplicationFiled: December 20, 2011Publication date: August 9, 2012Applicant: FUJITSU LIMITEDInventors: Keishiro OKAMOTO, Tadahiro Imada, Nobuhiro Imaizumi, Keiji Watanabe