Patents by Inventor Keisuke Aoyagi

Keisuke Aoyagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080218241
    Abstract: In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on.
    Type: Application
    Filed: April 24, 2008
    Publication date: September 11, 2008
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Hideo NAGANO, Keisuke AOYAGI, Masao SUZUKI
  • Patent number: 7382160
    Abstract: In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: June 3, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hideo Nagano, Keisuke Aoyagi, Masao Suzuki
  • Publication number: 20070210868
    Abstract: In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on.
    Type: Application
    Filed: May 8, 2007
    Publication date: September 13, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Hideo Nagano, Keisuke Aoyagi, Masao Suzuki
  • Patent number: 7227410
    Abstract: In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: June 5, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hideo Nagano, Keisuke Aoyagi, Masao Suzuki
  • Publication number: 20050231282
    Abstract: In a differential output circuit, a second amplifier has a positive terminal connected to a second fixed potential and a negative terminal to a fifth switch at a first terminal. First and second switches are connected at a point connected to the fifth switch at a second terminal and to a first load. Third and fourth switches are connected at a point connected to the fifth switch at a third terminal and to a second load. The second terminal is connected to the first terminal when the second and third switches turn on. The third terminal is connected to the first terminal when the first and fourth switches turn on.
    Type: Application
    Filed: April 12, 2005
    Publication date: October 20, 2005
    Inventors: Hideo Nagano, Keisuke Aoyagi, Masao Suzuki
  • Patent number: 6335696
    Abstract: A parallel-serial conversion circuit includes a frequency divider circuit which outputs a dichotomized signal of an input clock signal. A positive edge triggered flip-flop and a negative edge triggered flip-flop receive data and the dichotomized signal is input. A tap signal generator receives the clock signal and generates and outputs a series of tap signals by providing different delays to the clock signal. A selection signal generator receives the tap signals and generates a series of pulse signals having the width equivalent to 1 bit of serial data. An inverter circuit inverts the dichotomized signal. A 10-bit parallel-serial converter receives data from of the flip-flops, a signal of the inverter circuit, and the pulse signals. The 10-bit parallel-serial converter performs parallel to serial conversion based on the input data and signals and outputs the serial data.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: January 1, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Keisuke Aoyagi, Atsushi Sakamoto
  • Patent number: D785753
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: May 2, 2017
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Keisuke Aoyagi, Yukiko Ichinose, Maki Hirakawa