Patents by Inventor Keisuke Bekki

Keisuke Bekki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6513131
    Abstract: A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.
    Type: Grant
    Filed: August 19, 1999
    Date of Patent: January 28, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Shoji Suzuki, Yoshimichi Sato, Korefumi Tashiro, Keisuke Bekki, Hiroshi Sato, Makoto Nohmi, Shinya Ohtsuji
  • Patent number: 6092217
    Abstract: A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing means provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also comprises comparison means for comparing a signal output of the synthesizing means with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.
    Type: Grant
    Filed: November 3, 1997
    Date of Patent: July 18, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Shoji Suzuki, Yoshimichi Sato, Korefumi Tashiro, Keisuke Bekki, Hiroshi Sato, Makoto Nohmi, Shinya Ohtsuji
  • Patent number: 5805134
    Abstract: A highly reliable display control apparatus and method suitable for use in a computer control system which is required to have high degree of reliability, such as control systems for railroad traffic or a nuclear power station. A meaningful symbol is divided into a plurality of sections and these sections are independently input to either one of the inputs of an interactive man-machine system through different systems so that these sections of the meaningful symbol are displayed in the same frame of the man-machine system, thus enabling the operator to visually detect any abnormality as to whether the displayed meaningful symbol is complete or not, whereby a high degree of reliability of the display is obtained.
    Type: Grant
    Filed: February 26, 1996
    Date of Patent: September 8, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Seki, Nobuhisa Kobayashi, Keisuke Bekki
  • Patent number: 5802266
    Abstract: A self-checking circuit, which is useful for a highly reliable system configuration, includes a logic circuit having an error detection function. For function blocks for feeding out a plurality of signals that are at least duplexed, the logic circuit compares the output signals of the function blocks, and detects an error on the basis of results of the comparison. The logic circuit comprises synthesizing circuitry provided to superimpose inherent waveforms assigned in advance to the respective output signals of the function blocks onto the output signals of one of the function blocks. The inherent waveforms are orthogonal waveforms generated by an orthogonal waveform generator circuit. The logic circuit also compares the output signals having the superimposed inherent waveforms with the signal output of the other function block to detect an error. The whole circuit including the function blocks are judged normal only if the waveforms inherent to both output signals exist.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: September 1, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Nobuyasu Kanekawa, Shoji Suzuki, Yoshimichi Sato, Korefumi Tashiro, Keisuke Bekki, Hiroshi Sato, Makoto Nohmi, Shinya Ohtsuji
  • Patent number: 5422965
    Abstract: An air bag operation device which employs only one CPU module to guarantee sufficient fail-safety in the operation of the air bag without increasing the scale of the hardware. A plurality of crash-discriminating programs of different versions and a plurality of self-diagnosing programs of different versions are executed by a single CPU module, a signal is fed to an air bag igniting device based upon a comparison of the discriminated results by the plurality of crash-discriminating programs, and a signal is fed to an abnormality alarm device based upon comparison of the discriminated results of the plurality of self-diagnosing programs.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: June 6, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Keisuke Bekki, Hiroshi Sato, Korefumi Tashiro, Seiko Suzuki, Masayoshi Suzuki
  • Patent number: 5065335
    Abstract: A decoding type select logic generating method includes the steps of listing on a group basis input signal names and output destination signal names contained in register transfer descriptions and control codes for commanding execution of the register transfers for each of the same input signal names and same output destination signal names, simplifying logics by replacing the control code having the hamming distance of one by a bit meaning "don't care" on the group basis, generating AND gates for the control codes and the input signal names in each of the groups having the same input signal name and combining the outputs of the AND gates, generating AND gates for the control codes in each group having the same output destination signal name and combining the outputs of the AND gates for each of the output destination signal names, and combining the outputs of the groups each having the same input signal name and the groups each having the same output destination signal name.
    Type: Grant
    Filed: March 15, 1989
    Date of Patent: November 12, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Takayoshi Yokota, Keisuke Bekki, Nobuhiro Hamada
  • Patent number: 4964056
    Abstract: An automatic design system of a logic circuit system includes a storage for storing information about structures and functions of known basic circuits available for a circuit system to be designed, an input device for receiving design specification information about the structures and functions of the circuit to be designed, and a synthesize section for combining the known basic circuits stored in the storage so as to synthesize the desired logic circuit satisfying the design specification information.
    Type: Grant
    Filed: March 24, 1988
    Date of Patent: October 16, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Keisuke Bekki, Takayoshi Yokota, Tooru Nagai, Nobuhiro Hamada
  • Patent number: 4937755
    Abstract: A production system for an expert system comprising: a production rule memory unit storing circuit conversion rules, each having a condition part describing circuit connection and an execution part describing a conversion of the condition part to an equivalent logic circuit dependent upon a predetermined semiconductor technology and further having a provisionally predetermined priority; a task data memory unit storing circuit connection data, each being subjected to an application of the circuit conversion rules; a production rule interpretation and execution unit for selecting a circuit conversion rule in accordance with the provisionally predetermined priority, collating the condition part of the selected circuit conversion rule with the circuit connection data to determine whether the condition part matches with a part of the circuit connection data and, when the both match each other, converting the part of the circuit connection data by the corresponding execution part of the circuit conversion rule to a
    Type: Grant
    Filed: April 28, 1988
    Date of Patent: June 26, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Takayoshi Yokota, Keisuke Bekki, Nobuhiro Hamada