Abstract: A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

Abstract: The present disclosure provides a chip part. The chip part includes: a substrate, a first external electrode and a second external electrode, a capacitor portion disposed on a first main surface of the substrate, a lower electrode including a drawer portion drawn out to the first main surface, a capacitive film disposed on the lower electrode, an upper electrode disposed on the capacitive film, a first electrode film electrically connecting the first external electrode to the lower electrode, and a second electrode film electrically connecting the second external electrode to the upper electrode. The drawer portion includes a first portion disposed in a region between the first external electrode and the second external electrode, and the first electrode film includes a first lower contact portion connected to the first portion.

Abstract: The present disclosure provides a chip part. The chip part is capable of ensuring a greater capacitance of a capacitor, maintaining stability of walls and enhancing stability of components. The chip part includes: a substrate, having a first main surface and a second main surface opposite to the first main surface; a capacitive film, disposed on the first main surface; a first external electrode, disposed on the capacitive film; a second external electrode, disposed on the second main surface; and a conductive layer, disposed between the capacitive film and the substrate. A vertical capacitor having a laminated structure of an upper electrode (first external electrode)-capacitive film-lower electrode (substrate) is formed in a lengthwise direction along the thickness direction of the substrate.

Abstract: The present disclosure provides a chip part. The chip part includes a substrate, a first external electrode, a second external electrode, a capacitor portion, a lower electrode, a capacitive film and an upper electrode. The first external electrode and the second external electrode are disposed on a first main surface of the substrate. The capacitor portion is disposed on the first main surface of the substrate. The lower electrode includes a first body portion and a first peripheral portion integrally drawn out around the capacitor portion from the first body portion. The capacitive film includes a second body portion disposed within the capacitor portion and a second peripheral portion integrally drawn out from the second body portion to the first peripheral portion. The upper electrode is disposed on the capacitive film.

Abstract: The present disclosure provides a chip part. The chip part includes a substrate, a capacitor portion and a substrate body portion. The capacitor portion includes a plurality of wall portions having a lengthwise direction and separated from each other by a trench formed on a first main surface of the substrate. The substrate body portion is formed around the capacitor portion using a portion of the substrate. The plurality of wall portions are formed of a plurality of pillar units. The capacitor portion, in the plan view, includes a first capacitor portion and a second capacitor portion. The first capacitor portion includes the plurality of wall portions having the lengthwise direction as a first lengthwise direction. The second capacitor portion includes the plurality of wall portions having the lengthwise direction as a second lengthwise direction orthogonal to the first lengthwise direction.

Abstract: The present disclosure provides a chip part. The chip part includes: a capacitor portion, including a plurality of wall portions separated from each other by a plurality of trenches formed on the first main surface and having a lengthwise direction; a substrate body, formed around the capacitor portion using a portion of the semiconductor substrate; a lower electrode, disposed using at least a portion of the semiconductor substrate including the wall portions; a capacitive film, disposed along top and side surfaces of the plurality of wall portions; and an upper electrode, disposed on the capacitive film.

Abstract: The present disclosure provides a chip part. The chip part includes: a substrate, having a first main surface and a second main surface opposite to the first main surface; a capacitive film, disposed on the first main surface; a plurality of first external electrodes, disposed on the capacitive film and separated from each other; a second external electrode, disposed on the second main surface; a resistance layer, disposed between the capacitive film and the plurality of first external electrodes, and formed across the plurality of first external electrodes.

Abstract: A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

Abstract: A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

Abstract: A chip component includes a substrate that has a first surface and a second surface on a side opposite to the first surface, a plurality of wall portions that are formed on a side of the first surface by using a part of the substrate, that have one end portion and one other end portion, and that are formed of a plurality of pillar units, a support portion that is formed around the wall portions by using a part of the substrate and that is connected to at least one of the end portion and the other end portion of the wall portions, and a capacitor portion formed by following a surface of the wall portion, in which each of the pillar units includes a central portion and three convex portions that extend from the central portion in three mutually different directions in a plan view and in which the wall portion is formed by a connection between the convex portions of the pillar units that adjoin each other.

Abstract: A filter chip includes a substrate, a plurality of external terminals formed on the substrate for external connection, and a plurality of passive element forming regions provided in the regions between the plurality of external terminals in plan view when viewed along a direction normal to the surface of the substrate, the plurality of passive element forming regions including at least a resistor forming region where a resistor is formed. The resistor forming region includes a resistive conductive film formed on the substrate with one end and the other end thereof electrically connected to different ones of the external terminals, and a fuse portion integrally formed with the resistive conductive film. The fuse portion is cuttably provided to electrically connect a part of the resistive conductive film to the external terminals, or to electrically separate a part of the resistive conductive film from the external terminals.

Abstract: A filter chip includes a substrate, a plurality of external terminals formed on the substrate for external connection, and a plurality of passive element forming regions provided in the regions between the plurality of external terminals in plan view when viewed along a direction normal to the surface of the substrate, the plurality of passive element forming regions including at least a resistor forming region where a resistor is formed. The resistor forming region includes a resistive conductive film formed on the substrate with one end and the other end thereof electrically connected to different ones of the external terminals, and a fuse portion integrally formed with the resistive conductive film. The fuse portion is cuttably provided to electrically connect a part of the resistive conductive film to the external terminals, or to electrically separate a part of the resistive conductive film from the external terminals.

Abstract: The inductance device (4) includes: a magnetic metal substrate (2) comprising a metallic substrate (10) having first permeability, a first insulating layer (16a) disposed in the metallic substrate (10), and a first metallic wiring layer (22) having second permeability and disposed on the first insulating layer (16a); a first gap layer (24) disposed on the front side surface of the magnetic metal substrate (2); and a first magnetic flux generation layer (26) disposed on the first gap layer (24). There are provide a thin magnetic metal substrate adaptable to the large current use and advantageous in the high frequency characteristics; and an inductance device to which such a magnetic metal substrate are applied, wherein the inductance device is adaptable to smaller mounting area, larger inductance values, and large current use and advantageous in high frequency characteristics.