Patents by Inventor Keisuke Funatsu

Keisuke Funatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240077493
    Abstract: Provided is a non-transitory computer-readable medium storing a program for causing a computer to execute the steps including a step of subjecting a sample containing microorganisms to mass spectrometry to obtain a mass spectrum, a step of reading a mass-to-charge ratio m/z of a peak derived from a marker protein from the mass spectrum, and an identification step of identifying which bacteria of serovar of Salmonella genus bacteria the microorganisms contained in the sample contain, based on the mass-to-charge ratio m/z, wherein at least one of two types of ribosomal proteins S8 and Peptidylpropyl isomerase is used as the marker protein.
    Type: Application
    Filed: July 13, 2023
    Publication date: March 7, 2024
    Applicants: SHIMADZU Corporation, Meijo University
    Inventors: Hiroto Tamura, Naomi Yamamoto, Teruyo Kato, Keisuke Shima, Shinji Funatsu
  • Patent number: 6894334
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: May 17, 2005
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 6734104
    Abstract: Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 11, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Kazusato Hara, Keisuke Funatsu, Toshinori Imai, Junji Noguchi, Naohumi Ohashi
  • Publication number: 20030189255
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Application
    Filed: March 3, 2003
    Publication date: October 9, 2003
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Publication number: 20030073317
    Abstract: Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.
    Type: Application
    Filed: November 19, 2002
    Publication date: April 17, 2003
    Inventors: Kazusato Hara, Keisuke Funatsu, Toshinori Imai, Junji Noguchi, Naohumi Ohashi
  • Patent number: 6548847
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: April 15, 2003
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 6495466
    Abstract: Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: December 17, 2002
    Assignee: Hitachi Ltd.
    Inventors: Kazusato Hara, Keisuke Funatsu, Toshinori Imai, Junji Noguchi, Naohumi Ohashi
  • Publication number: 20020017669
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Application
    Filed: July 9, 2001
    Publication date: February 14, 2002
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 6342412
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: January 29, 2002
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Publication number: 20010034132
    Abstract: Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.
    Type: Application
    Filed: April 3, 2001
    Publication date: October 25, 2001
    Inventors: Kazusato Hara, Keisuke Funatsu, Toshinori Imai, Junji Noguchi, Naohumi Ohashi
  • Patent number: 6169324
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: January 2, 2001
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 6127255
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: October 3, 2000
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 5811316
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 22, 1998
    Assignees: Hitachi. Ltd., Hitachi VLSI Engineering Corporation
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 5780882
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: June 1, 1995
    Date of Patent: July 14, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 5739589
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: June 3, 1996
    Date of Patent: April 14, 1998
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 5557147
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: September 17, 1996
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corporation
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 5503708
    Abstract: An organic film removing method uses an organic film removing apparatus comprising a processing vessel defining a processing chamber, a wafer support for supporting a semiconductor wafer within the processing chamber, and a mixed gas supplier for supplying a mixed gas consisting of an alcohol or alcohols, and ozone gas or an ozone-containing gas into the processing chamber so that the mixed gas acts on an organic film pattern on the surface of the supported semiconductor wafer.
    Type: Grant
    Filed: November 23, 1993
    Date of Patent: April 2, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Kootaroo Koizumi, Sukeyoshi Tsunekawa, Kenichi Kawasumi, Takeshi Kimura, Keisuke Funatsu
  • Patent number: 5478401
    Abstract: An apparatus and method for surface treatment of a substance to be processed, which are capable of decreasing the number of foreign matters holding on the reverse side of the substance more than prior art like apparatus and method without largely decreasing a surface treating speed as compared with that of the prior art, by supplying ozone gas to the surface of the substance mounted on a supporting base. The supporting base has a heating part and a supporting part. There is provided a supporting material on the surface of the supporting part for partly supporting one side of the substance to be processed so that a required amount of gap may be formed between the substance to be processed and the supporting part. In the heating part is built a heater. And for a member constituting the supporting part is used a material having greater emissivity than a member constituting the heating part.
    Type: Grant
    Filed: March 7, 1995
    Date of Patent: December 26, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Sukeyoshi Tsunekawa, Keisuke Funatsu, Kenichi Kawasumi, Akio Inada, Masaro Kaku
  • Patent number: 5331191
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: July 19, 1994
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 5202275
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: April 13, 1993
    Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane