Patents by Inventor Keisuke FURUYA

Keisuke FURUYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11945962
    Abstract: The present invention provides a cationic electrodeposition coating composition that has both good anti-cissing property and good coating film appearance. This is a cationic electrodeposition coating composition containing a silicone compound (A) having an SP value of more than 10.5 and 15.0 or less, and a film forming resin (B), wherein the silicone compound (A) is contained in an amount of 0.01 parts by mass or more and 4.5 parts by mass or less per 100 parts by mass of the resin solid content of the film forming resin (B). For example, the silicone compound (A) is at least one species selected from the group consisting of a polyether modified silicone compound (A-1), a polyester modified silicone compound (A-2), and a polyacrylic modified silicone compound (A-3).
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: April 2, 2024
    Assignee: NIPPON PAINT AUTOMOTIVE COATINGS CO., LTD.
    Inventors: Masayuki Kotani, Yuko Hasegawa, Yasuyuki Furuya, Keigo Obata, Keisuke Tsutsui, Hiroki Arai, Hiroyoshi Yamazaki
  • Publication number: 20240084164
    Abstract: The present invention provides a cationic electrodeposition coating composition that has both good anti-cissing property and good coating film appearance. This is a cationic electrodeposition coating composition containing a silicone compound (A) having an SP value of more than 10.5 and 15.0 or less, and a film forming resin (B), wherein the silicone compound (A) is contained in an amount of 0.01 parts by mass or more and 4.5 parts by mass or less per 100 parts by mass of the resin solid content of the film forming resin (B). For example, the silicone compound (A) is at least one species selected from the group consisting of a polyether modified silicone compound (A-1), a polyester modified silicone compound (A-2), and a polyacrylic modified silicone compound (A-3).
    Type: Application
    Filed: November 9, 2023
    Publication date: March 14, 2024
    Applicant: NIPPON PAINT AUTOMOTIVE COATINGS CO., LTD.
    Inventors: Masayuki KOTANI, Yuko HASEGAWA, Yasuyuki FURUYA, Keigo OBATA, Keisuke TSUTSUI, Hiroki ARAI, Hiroyoshi YAMAZAKI
  • Patent number: 9397160
    Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.
    Type: Grant
    Filed: September 3, 2015
    Date of Patent: July 19, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshinori Yoshida, Hirokazu Kato, Tsuyoshi Kachi, Keisuke Furuya
  • Publication number: 20150380487
    Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.
    Type: Application
    Filed: September 3, 2015
    Publication date: December 31, 2015
    Inventors: Yoshinori Yoshida, Hirokazi Kato, Tsuyoshi Kachi, Keisuke Furuya
  • Patent number: 9142555
    Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: September 22, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinori Yoshida, Hirokazu Kato, Tsuyoshi Kachi, Keisuke Furuya
  • Publication number: 20150145025
    Abstract: Provided is a semiconductor device having improved performance. A semiconductor substrate is formed with unit LDMOSFET elements. The unit LDMOSFET elements have respective source regions electrically coupled to each other via a first source interconnect line and a second source interconnect line. The unit LDMOSFET elements have respective gate electrodes electrically coupled to each other via a first gate interconnect line and also electrically coupled to a second gate interconnect line in the same layer as that of the second source interconnect line via the first gate interconnect line. The unit LDMOSFET elements have respective drain regions electrically coupled to a back surface electrode via a conductive plug embedded in a trench of the semiconductor substrate. Each of the first source interconnect line and the first gate interconnect line has a thickness smaller than that of the second source interconnect line. Over the plug, the first gate interconnect line extends.
    Type: Application
    Filed: November 20, 2014
    Publication date: May 28, 2015
    Inventors: YOSHINORI YOSHIDA, HIROKAZU KATO, TSUYOSHI KACHI, Keisuke FURUYA