Abstract: A roadable vehicle includes main wings, a fuselage, a sliding door on a lateral side surface of the fuselage, and hinge mechanisms. The hinge mechanisms connect the main wings to the fuselage. The hinge mechanisms allow the main wings to turn between a first state where the main wings are folded beside the fuselage and a second state where the main wings are opened on the lateral sides of the fuselage. In the first state, the sliding door is opened and closed by sliding the sliding door in a space formed between one of the main wings and the fuselage while an outer side of the fuselage and an inner side of the sliding door facing each other.

Abstract: A position detection device includes a first position detector, a second position detector, and a signal generator. The first position detector includes a first magnetic field generation unit, a second magnetic field generation unit, and a first magnetic sensor. The second position detector includes a third magnetic field generation unit, a fourth magnetic field generation unit, and a second magnetic sensor. The positions of the second and fourth magnetic field generation units vary in response to variations in a detection-target position. The signal generator generates a position detection signal, which is the sum of a first detection signal generated by the first magnetic sensor and a second detection signal generated by the second magnetic sensor. Each of the first and second position detectors includes a bias magnetic field generation unit.

Abstract: There is provided an exhaust gas purification device that shows a high HC removal performance under a condition in which a rich air-fuel mixture is introduced. The exhaust gas purification device includes a substrate, a first catalyst layer, and a second catalyst layer. The substrate includes an upstream end and a downstream end. The first catalyst layer is disposed on a surface of the partition wall in an upstream region including the upstream end of the substrate. The second catalyst layer is disposed inside the partition wall in a downstream region including the downstream end of the substrate. The first catalyst layer contains a first metal catalyst and alumina-zirconia composite oxide. The second catalyst layer contains a second metal catalyst.

Abstract: The magnetic sensor can prevent an increase of a positional detection error of a subject/object even in the case of applying an external magnetic field with a magnetic field intensity exceeding a predetermined range. A magnetic sensor is equipped with a magnetoresistive effect element (MR element) 11 that can detect an external magnetic field and a soft magnetic body shield 12. The soft magnetic body shield(s) 12 are/is positioned above and/or below the MR element 11 in a side view, and the size of the MR element 11 is physically included within a perimeter of the soft magnetic body shield 12.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern.

Abstract: A method of placing a dummy pattern in a wiring region includes calculating a density of a wiring pattern in the wiring region and calculating a value of a length of a periphery of the wiring pattern. The dummy pattern is then set such that a total of the pattern density and the value of the length of the periphery of the wiring pattern and the dummy pattern in the wiring region falls within specified ranges in the wiring region.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern.

Abstract: Provided is a method of predicting a manufacturing defect part of a semiconductor device, which results from optical pattern displacement in an exposure process. The prediction method includes: performing repetitive processing a plurality of times, the repetitive processing including: a site generating step of setting a site at a predetermined position of a layout pattern; an edge shifting step of shifting an edge of the layout pattern according to a predetermined rule; an image forming position calculating step of calculating an image forming position corresponding to the shifted edge on the site; and an error check step of storing error information between the image forming position on the site and the edge of the layout pattern; and extracting, based on the error information, from the first layout data, apart in which the image forming position is unstable, and predicting the extracted part as a hot spot.

Abstract: A semiconductor element, a semiconductor sensor, and a semiconductor memory element are provided, in which an MFMIS structure having a lower electrode and an integrated circuit can be integrated. An epitaxially grown ?-Al2O3 single crystal film (2) is disposed on a semiconductor single crystal substrate (1), and an epitaxial single crystal Pt thin film (3) is disposed on the ?-Al2O3 single crystal film (2).

Abstract: An integrated device including a sensor and the like formed on a ?-alumina layer epitaxially grown on a silicon substrate is provided at low cost. This integrated device includes: a silicon substrate; a first function area formed on a ?-alumina film epitaxially grown on a portion of the silicon substrate; a second function area formed on an area of the silicon substrate other than an area where the ?-alumina film is grown; and wiring means for connecting the first function area with the second function area.

Abstract: A method of placing a dummy pattern in a wiring region includes calculating a density of a wiring pattern in the wiring region and calculating a value of a length of a periphery of the wiring pattern. The dummy pattern is then set such that a total of the pattern density and the value of the length of the periphery of the wiring pattern and the dummy pattern in the wiring region falls within specified ranges in the wiring region.

Abstract: A semiconductor element, a semiconductor sensor, and a semiconductor memory element are provided, in which an MFMIS structure having a lower electrode and an integrated circuit can be integrated. An epitaxially grown ?-Al2O3 single crystal film (2) is disposed on a semiconductor single crystal substrate (1), and an epitaxial single crystal Pt thin film (3) is disposed on the ?-Al2O3 single crystal film (2).