Abstract: A magnetic sensor includes a first insulating layer, a second insulating layer, a third insulating layer, a lower coil element located on an opposite side of the first insulating layer from the second insulating layer, and a second MR element. The second MR element includes a magnetization pinned layer and a free layer. The magnetization pinned layer and the free layer are located on an opposite side of the third insulating layer from the second insulating layer. The first and third insulating layers each contain a first insulating material. The second insulating layer contains a second insulating material.

Abstract: A wall-flow type particulate filter includes: a wall-flow type base material; and a coat layer formed on the base material. The base material includes: an inlet cell open only at an exhaust gas inlet end; an outlet cell open only at an exhaust gas outlet end; and a partition partitioning the inlet and outlet cells and having multiple pores through which the inlet and outlet cells communicate with each other. The coat layer is provided for the wall surfaces of the pores and contains a first inorganic oxide and a second inorganic oxide. The mean particle diameter Da of the first inorganic oxide is larger than the mean particle diameter Db of the second inorganic oxide. The weight ratio of the second inorganic oxide is designed to be from 10% to 50% inclusive when the total weight ratio of the first inorganic oxide and the second inorganic oxide is 100%.

Abstract: A method of manufacturing a composite includes bringing a first surface of a first base in which a first fiber base that is to constitute the first base is impregnated with a first resin into contact with a second surface of a second base in which a second fiber base that is to constitute the second base is not impregnated with a second resin, and impregnating the second fiber base with a portion of the first resin with which the first fiber base is impregnated.

Abstract: An exhaust gas purification device suppresses a pressure loss increase and includes a honeycomb substrate and inflow cell side catalyst layer. The substrate includes a porous partition wall defining several cells extending from an inflow side end surface to an outflow side end surface. The cells include an inflow and outflow cell adjacent across the wall. The inflow cell has an open inflow side end and sealed outflow side end. The outflow cell has a sealed inflow side end and open outflow side end. The catalyst layer is on an inflow cell side surface in an region extending from the inflow side end positioned 10% or more of the partition wall length. At this position, a filled portion of the inflow cell side catalyst layer pores are 40% or less. The pores are present to a depth of 50% of a thickness of the partition wall.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern.

Abstract: A method of placing a dummy pattern in a wiring region includes calculating a density of a wiring pattern in the wiring region and calculating a value of a length of a periphery of the wiring pattern. The dummy pattern is then set such that a total of the pattern density and the value of the length of the periphery of the wiring pattern and the dummy pattern in the wiring region falls within specified ranges in the wiring region.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern.

Abstract: Provided is a method of predicting a manufacturing defect part of a semiconductor device, which results from optical pattern displacement in an exposure process. The prediction method includes: performing repetitive processing a plurality of times, the repetitive processing including: a site generating step of setting a site at a predetermined position of a layout pattern; an edge shifting step of shifting an edge of the layout pattern according to a predetermined rule; an image forming position calculating step of calculating an image forming position corresponding to the shifted edge on the site; and an error check step of storing error information between the image forming position on the site and the edge of the layout pattern; and extracting, based on the error information, from the first layout data, apart in which the image forming position is unstable, and predicting the extracted part as a hot spot.

Abstract: A semiconductor element, a semiconductor sensor, and a semiconductor memory element are provided, in which an MFMIS structure having a lower electrode and an integrated circuit can be integrated. An epitaxially grown ?-Al2O3 single crystal film (2) is disposed on a semiconductor single crystal substrate (1), and an epitaxial single crystal Pt thin film (3) is disposed on the ?-Al2O3 single crystal film (2).

Abstract: An integrated device including a sensor and the like formed on a ?-alumina layer epitaxially grown on a silicon substrate is provided at low cost. This integrated device includes: a silicon substrate; a first function area formed on a ?-alumina film epitaxially grown on a portion of the silicon substrate; a second function area formed on an area of the silicon substrate other than an area where the ?-alumina film is grown; and wiring means for connecting the first function area with the second function area.

Abstract: A method of placing a dummy pattern in a wiring region includes calculating a density of a wiring pattern in the wiring region and calculating a value of a length of a periphery of the wiring pattern. The dummy pattern is then set such that a total of the pattern density and the value of the length of the periphery of the wiring pattern and the dummy pattern in the wiring region falls within specified ranges in the wiring region.

Abstract: A semiconductor element, a semiconductor sensor, and a semiconductor memory element are provided, in which an MFMIS structure having a lower electrode and an integrated circuit can be integrated. An epitaxially grown ?-Al2O3 single crystal film (2) is disposed on a semiconductor single crystal substrate (1), and an epitaxial single crystal Pt thin film (3) is disposed on the ?-Al2O3 single crystal film (2).