Abstract: A computer-readable recording medium on which is recorded a program, which is used by a computer for estimating a critical path among a plurality of paths given as paths within an integrated circuit, for causing the computer to execute a process, the process comprising receiving from a memory inputs of a logic description for the integrated circuit, and the plurality of given paths, obtaining a path evaluation value, which represents a delay of a path, for each of the given paths, and prioritizing the paths according to evaluation values, and estimating a path having a large evaluation value as the critical path.

Abstract: The present invention provides a logic-synthesis method and a logic synthesizer that can estimate the performance of an LSI circuit during the RTL-design phase. The logic-synthesis method includes the steps of generating a library having a buffer-tree-characteristic description, determining the position where the fanout value is high by analyzing a logic-design description, specifying the configuration of a buffer tree including the high fanout position, and performing logic synthesis according to the logic-design description.

Abstract: A computer-readable recording medium on which is recorded a program, which is used by a computer for estimating a critical path among a plurality of paths given as paths within an integrated circuit, for causing the computer to execute a process, the process comprising receiving from a memory inputs of a logic description for the integrated circuit, and the plurality of given paths, obtaining a path evaluation value, which represents a delay of a path, for each of the given paths, and prioritizing the paths according to evaluation values, and estimating a path having a large evaluation value as the critical path.

Abstract: The present invention provides a logic-synthesis method and a logic synthesizer that can estimate the performance of an LSI circuit during the RTL-design phase. The logic-synthesis method includes the steps of generating a library having a buffer-tree-characteristic description, determining the position where the fanout value is high by analyzing a logic-design description, specifying the configuration of a buffer tree including the high fanout position, and performing logic synthesis according to the logic-design description.

Abstract: A hierarchical routing method is implemented in a layout system for a semiconductor integrated circuit which has a repetitive circuit portion. The hierarchical routing method lays out circuit elements for the repetitive circuit portion with the repetitive circuit portion structured hierarchically, expands the layout for the hierarchically-structured repetitive circuit portion in a separate independent database, extracts information of connections from the expanded layout for the repetitive circuit portion, and then carries out routing. Therefore, a semiconductor integrated circuit having a repetitive circuit portion can be designed in a short period of time while excellent properties are ensured for the semiconductor integrated circuit.