Abstract: Provided are a hose excelling in a lightweight property and in fatigue fracture resistance, a method for manufacturing the hose, and a hydraulic pump. The hose includes a tube, an interior of the tube being hollow, continuous carbon fibers and/or continuous glass fibers wound around an outer circumference of the tube, and a thermosetting resin present external to the tube. The thermosetting resin has an elastic modulus from 0.5 to 10 MPa, and the continuous carbon fibers and/or continuous glass fibers are impregnated with at least a part of the thermosetting resin. The elastic modulus of the thermosetting resin is a numeric value determined by: heating the thermosetting resin for 2 hours at a curing temperature of the thermosetting resin; then subjecting the thermosetting resin to thermoregulation for two weeks under a condition of a temperature of 23° C. and a relative humidity of 55%; and then performing a measurement in accordance with JIS K7161:2019.

Abstract: A securing tool for a heat retention block covering a turbine casing main body includes: a securing rod, one end of which has an engaging portion with a protrusion; and a socket. The socket includes a guide groove, into which the protrusion of the securing rod is inserted, and a recessed groove. The guide groove includes a first guide groove, which extends in the socket axis direction from a starting end to a terminal end, and a second guide groove, the starting end of which is connected to the terminal end, and which extends from the starting end to a terminal end in a circumferential direction relative to the socket axis. The second guide groove is connected to the recessed groove.

Abstract: A securing tool for a heat retention block covering a turbine casing main body includes: a securing rod, one end of which has an engaging portion with a protrusion; and a socket. The socket includes a guide groove, into which the protrusion of the securing rod is inserted, and a recessed groove. The guide groove includes a first guide groove, which extends in the socket axis direction from a starting end to a terminal end, and a second guide groove, the starting end of which is connected to the terminal end, and which extends from the starting end to a terminal end in a circumferential direction relative to the socket axis. The second guide groove is connected to the recessed groove.

Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

Abstract: One of the upper surface and the lower surface of a semiconductor layer (7) of a thin-film transistor (101) in a semiconductor device (100) is in contact with a gate insulating layer (5), and the other is in contact with a first insulating layer (11) containing silicon oxide. The semiconductor layer (7) includes a first and second oxide semiconductor layers (7A, 7B). The first oxide semiconductor layer (7A) is arranged on a gate insulating layer side of the second oxide semiconductor layer (7B) and is in contact with the second oxide semiconductor layer. The second oxide semiconductor layer (7B) contains In and Ga and does not contain Sn. The first oxide semiconductor layer (7A) contains In, Sn, and Zn. The percentage of Zn in the first oxide semiconductor layer (7A) in the depth direction does not have a maximum value in the vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer.

Abstract: A semiconductor device includes, a plurality of oxide semiconductor TFTs including a first gate electrode, a first insulating layer in contact with the first gate electrode, an oxide semiconductor layer opposing the first gate electrode via the first insulating layer, a source electrode and a drain electrode which are connected with the oxide semiconductor layer, and an organic insulating layer covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT which is covered with the organic insulating layer and a second TFT which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode opposing the oxide semiconductor layer via a second insulating layer, the second gate electrode being arranged to overlap with at least a portion of the first gate electrode with the oxide semiconductor layer interposed therebetween.

Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

Abstract: One of the upper surface and the lower surface of a semiconductor layer (7) of a thin-film transistor (101) in a semiconductor device (100) is in contact with a gate insulating layer (5), and the other is in contact with a first insulating layer (11) containing silicon oxide. The semiconductor layer (7) includes a first and second oxide semiconductor layers (7A, 7B). The first oxide semiconductor layer (7A) is arranged on a gate insulating layer side of the second oxide semiconductor layer (7B) and is in contact with the second oxide semiconductor layer. The second oxide semiconductor layer (7B) contains In and Ga and does not contain Sn. The first oxide semiconductor layer (7A) contains In, Sn, and Zn. The percentage of Zn in the first oxide semiconductor layer (7A) in the depth direction does not have a maximum value in the vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer.

Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

Abstract: A semiconductor device (100A) includes a substrate (11); a TFT (10A) supported on the substrate, the TFT including an oxide semiconductor layer (16); an organic insulating layer (24) covering the TFT; a lower layer electrode (32) on the organic insulating layer; a dielectric layer (34) on the lower layer electrode; an upper layer electrode on the dielectric layer; and an upper layer electrode (36) including a portion opposing the lower layer electrode via the dielectric layer. The dielectric layer is a silicon nitride film having a hydrogen content of 5.33×1021 atoms/cm3 or less.

Abstract: A semiconductor device includes: a first substrate; a gate electrode on the first substrate; a gate insulating layer on the gate electrode; an oxide semiconductor film including a channel region disposed over the gate electrode through the gate insulating layer and lowered-resistance region contacting the channel region; a source electrode and a drain electrode on the channel region; a first insulating film covering at least the channel region and including a contact hole that exposes the lowered-resistance region; and a second insulating film having reducing characteristics and disposed above the first insulating film across the contact hole, the second insulating film contacting the lowered-resistance region inside the contact hole.

Abstract: A semiconductor device includes an oxide semiconductor film, a first insulating film, and a second insulating film. The oxide semiconductor film is made of oxide semiconductor material. The oxide semiconductor film includes a low resistance portion having an electrical resistance lower than another portion. The low resistance portion is separated from the other portion. The first insulating film is formed in an upper layer relative to the oxide semiconductor film. The first insulating film includes a hole at a position overlapping the low resistance portion. The second insulating film is formed in an upper layer relative to the first insulating film. The second insulating film and contains hydrogen.

Abstract: A semiconductor device includes: a first substrate; a gate electrode on the first substrate; a gate insulating layer on the gate electrode; an oxide semiconductor film including a channel region disposed over the gate electrode through the gate insulating layer and lowered-resistance region contacting the channel region; a source electrode and a drain electrode on the channel region; a first insulating film covering at least the channel region and including a contact hole that exposes the lowered-resistance region; and a second insulating film having reducing characteristics and disposed above the first insulating film across the contact hole, the second insulating film contacting the lowered-resistance region inside the contact hole.

Abstract: A semiconductor device includes a first conductive film, an insulating film, a second conductive film, and a semiconductor film. The insulating film is formed above the first conductive film such that the first conductive film includes an exposed portion that is exposed. The second conductive film is formed above the insulating film such that sides of the second conductive film are close to the exposed portion of the first conductive film. The semiconductor film includes a channel region for electrically connecting the second conductive film to the first conductive film via the channel region. The semiconductor film is formed above the second conductive film and across the exposed portion of the first conductive film from at least one side to another.

Abstract: A semiconductor device includes a substrate, a first thin film transistor supported on the substrate and having a first active layer that primarily contains a first oxide semiconductor, and second thin film transistor supported on the substrate and having a second active layer that primarily contains a second oxide semiconductor with a higher mobility than the first oxide semiconductor. The first active layer and the second active layer are positioned on the same insulating layer and contact the same insulating layer.

Abstract: A TFT substrate (100A) of a liquid crystal display panel includes: an organic interlayer insulating layer (24) covering a TFT; a first transparent electrically-conductive layer (25) provided in the first region of a surface of the organic interlayer insulating layer (24); and an inorganic dielectric layer (26) covering the first transparent electrically-conductive layer (25) and provided in a second region of the surface of the organic interlayer insulating layer (24) which is different from the first region, the inorganic dielectric layer (26) containing SiN, wherein an arithmetic mean roughness Ra of the first region and the second region of the surface of the organic interlayer insulating layer (24) is not less than 3.45 nm and not more than 5.20 nm.

Abstract: A semiconductor device (100) includes, on a substrate, a plurality of oxide semiconductor TFTs including a first gate electrode (12), a first insulating layer (20) which is in contact with the first gate electrode, an oxide semiconductor layer (16) arranged so as to oppose the first gate electrode via the first insulating layer, and a source electrode (14) and a drain electrode (15) which are connected with the oxide semiconductor layer, and an organic insulating layer (24) covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT (5A) which is covered with the organic insulating layer and a second TFT (5B) which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode (17) arranged so as to oppose the oxide semiconductor layer via a second insulating layer (22), when viewed in a direction normal to the substrate, the second gate electrode (17) being arranged so as to overlap with at least

Abstract: A semiconductor device (100) includes a substrate (11), a first TFT (10), and a second TFT (20). The first TFT includes a first semiconductor layer (12) that is supported by the substrate, a first gate electrode (14) that is formed on the first semiconductor layer and overlaps with the first semiconductor layer with a first gate insulating layer (13) interposed therebetween, a first insulating layer (16) that covers the first gate electrode, and a first source electrode (17s) and a first drain electrode (17d) that are formed on the first insulating layer and are connected to the first semiconductor layer.

Abstract: A TFT substrate (100A) of a liquid crystal display panel includes: an organic interlayer insulating layer (24) covering a TFT; a first transparent electrically-conductive layer (25) provided in the first region of a surface of the organic interlayer insulating layer (24); and an inorganic dielectric layer (26) covering the first transparent electrically-conductive layer (25) and provided in a second region of the surface of the organic interlayer insulating layer (24) which is different from the first region, the inorganic dielectric layer (26) containing SiN, wherein an arithmetic mean roughness Ra of the first region and the second region of the surface of the organic interlayer insulating layer (24) is not less than 3.45 nm and not more than 5.20 nm.

Abstract: A semiconductor device (100A) includes a substrate (11); a TFT (10A) supported on the substrate, the TFT including an oxide semiconductor layer (16); an organic insulating layer (24) covering the TFT; a lower layer electrode (32) on the organic insulating layer; a dielectric layer (34) on the lower layer electrode; an upper layer electrode on the dielectric layer; and an upper layer electrode (36) including a portion opposing the lower layer electrode via the dielectric layer. The dielectric layer is a silicon nitride film having a hydrogen content of 5.33×1021 atoms/cm3 or less.