Abstract: A photomultiplier tube 1 is an electron tube comprising an envelope 5 including a frame 3b having at least one end part formed with an opening and an upper substrate 2 airtightly joined to the opening, and a photocathode 6 contained within the envelope 5, the photocathode 6 emitting a photoelectron into the envelope 5 in response to light incident thereon from the outside; wherein multilayer metal films 10b, 10a each constituted by a metal film made of titanium, a metal film made of platinum, and a metal film made of gold laminated in this order are formed at the opening and the joint part between the upper substrate 2 and opening; and wherein the frame 3b and upper side substrate 2 are joined to each other by holding a joint layer 14 containing indium between the respective multilayer metal films 10b, 10a.

Abstract: Methods and apparatus are provided for executing processor tasks on a multi-processing system. The multi-processing system includes a plurality of sub-processing units and a main processing unit that may access a shared memory. Each sub-processing unit includes an on-chip local memory separate from the shared memory. The methods and apparatus contemplate: providing that the processor tasks be copied from the shared memory into the local memory of the sub-processing units in order to execute them, and prohibiting the execution of the processor tasks from the shared memory; and migrating at least one processor task from one of the sub-processing units to another of the sub-processing units.

Abstract: Enables efficient correction of topological consistency of an input three-dimensional shape approximated in a spatial graph. Structured mesh generation systems of the present invention include: a topology determination apparatus for reading shape data from a shape data storage device to determine topological consistency and outputting data for solving a problem about topological consistency; a decomposable shape generation apparatus for reading the data outputted by the topology determination apparatus, changing a constraint condition of an integer programming problem solver to execute a shape correction process and outputting corrected shape data; and a structured mesh generation apparatus for reading the corrected shape data to generate a structured mesh.

Abstract: An information processing apparatus/method allows a user to interactively combine a plurality of sound chips into music data, edit music data, and play it back, by inputting data or commands via a keyboard or a mouse. A chip such as a sound pattern, a one-shot patter, or an effect to be applied to a sound pattern or a one-shot pattern is assigned to each key of a keyboard. If a user presses a key, a chip corresponding to a pressed key is executed. When a plurality of keys are simultaneously pressed, corresponding chips are played in a superimposed fashion. A piece of music can be composed by sequentially pressing various keys thereby sequentially combining corresponding chips.

Abstract: A buffer is provided with a leading pointer and a following pointer. A bitmap in which two bits are assigned to each block is updated to retain which states blocks are in, busy, write-completed, or read-completed. Under the constraint that the two pointers move in the same direction and do not pass each other: after the block designated by the leading pointer starts to be written, the leading pointer is moved to a next block only if the next block is in the read-completed state; and after the block designated by the following pointer starts to be read, the following pointer is moved to a next block only if the next block is in the write-completed state.

Abstract: A recognition model generation system of the invention includes means 18 for labeling edges and faces of an input three-dimensional shape, means 20 for generating shape restriction values, shape restriction means 22 for restricting shape recognition using generated shape restriction values, and means 24 for generating position coordinates of vertexes of a shape that can be derived by substituting the input three-dimensional shape with hexahedrons using output from the shape restriction means. The invention also provides a method for generating a recognition model a program for causing a computer to execute the method, a computer-readable medium storing the program thereon, and a structured mesh generation system.

Abstract: The present invention provides methods, apparatus and systems to improve the quality of the arrangement of nodes in a graphics display, for which a graphics image consisting of nodes and arcs is generated, and to increase the processing speed. Nodes are sequentially added and arranged in a display space, and each time a new node is added, a predetermined dynamic model is employed to correct the locations of the new node and of nodes that were previously arranged in the display space. The nodes are arranged beginning with a node having numerous adjacent arcs, so that the nodes that are arranged early in the process are located nearer the center of the display space. In the graphics image thus formed in the display space, arcs located within a predetermined distance of a specific node are curved so they detour around the node.

Abstract: Thread information is retained in a main memory. The thread information includes a bit string and last executed information. Each bit of the bit string is allocated to a thread, and the number and the value of the bit indicate the number of the thread and whether or not the thread is in an executable state, respectively. The last executed information is the number of a last executed thread. A processor rotates the bit string so that a bit indicating the last executed thread comes to the end of the bit string. It searches the rotated bit string for a bit corresponding to a thread in the executable state in succession from the top, and selects the number of the first obtained bit as the number of the next thread to be executed. Then, the thread information is updated by changing the value of the bit of this number to indicate not being executable, and setting the last executed information to the number of this bit. This operation is performed by using an atomic command.

Abstract: The conveying device of the present invention comprises a cylindrical first roller, a cylindrical second roller that has a surface hardness higher than a surface hardness of the first roller, and a belt placed in a state surrounding either the first roller or the second roller. The conveying device moves an object to be conveyed by bringing the first roller and the second roller in pressure contact with each other via the belt and making the object pass through a nip portion formed of the belt and the first roller or the second roller facing the belt. A length in a lengthwise direction of an outer peripheral portion of the first roller is shorter than a length in a lengthwise direction of an outer peripheral portion of the second roller.

Abstract: Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object.

Abstract: Enables efficient correction of topological consistency of an input three-dimensional shape approximated in a spatial graph. Structured mesh generation systems of the present invention include: a topology determination apparatus for reading shape data from a shape data storage device to determine topological consistency and outputting data for solving a problem about topological consistency; a decomposable shape generation apparatus for reading the data outputted by the topology determination apparatus, changing a constraint condition of an integer programming problem solver to execute a shape correction process and outputting corrected shape data; and a structured mesh generation apparatus for reading the corrected shape data to generate a structured mesh.

Abstract: The invention implements inter-terminal transmission with guaranteed capacity based on the single-path configuration function of networks composed of switching hubs with an MAC address learning function and centralized management of transmission capacity, without control over hubs. The capacity to be used by transmission links on a network is stored in advance and transmission capacity along the path to be used is allocated based on requests from terminals, with the allocation removed using a Terminate Request. At such time, by using transmission links and switching hubs with an MAC address learning function, transmission is limited to single-path transmission.

Abstract: A synchronization scheme is provided for a multiprocessor system. In particular, a processor includes a buffer sync controller. The buffer sync controller is operative to allow or deny access by a subprocessor to shared data in a shared memory, such that a processor seeking to write data into or read data from the shared memory must ascertain certain shared parameter data processed by the buffer sync controller.

Abstract: Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.

Abstract: Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object.

Abstract: Methods and apparatus provide for associating memory allocation table (MAT) entries with nodes in a binary tree such that the nodes and the entries are grouped into hierarchical levels, each entry including status information; associating the nodes and the entries with segments of a shared memory of a multi-processor system such that higher level nodes and entries are associated with larger numbers of segments of the shared memory and lower level nodes and entries are associated with smaller numbers of segments of the shared memory; initializing the MAT such that the status information of at least a plurality of entries indicates that the associated segment or segments of the shared memory are available for reservation; and selecting one entry in a group of entries in the MAT at a level corresponding to a desired size of the shared memory to be reserved.

Abstract: Direct memory access is provided for each member of a group of IO devices organized into groups. Direct memory access for each IO device is performed in a predetermined order based on the predetermined groups, and may be completed by notification by an interrupt request. A predetermined time delay may be specified between each memory access by each IO device of a predetermined group.

Abstract: The present invention provides apparatus and methods to perform thermal management in a computing environment. Thermal attributes are associated with operations and/or processing components. The components have thermal thresholds that should not be exceeded. In a preferred embodiment, an operation can be transferred from one component to another component if the thermal threshold is exceeded during execution by the first component.

Abstract: A multiprocessor system and method wherein one of the processors is assigned the responsibility of handling interrupts and identifying the next processor to handle an interrupt. When that processor switches tasks and determines that it is no longer the least important processor as far as task priority is concerned, it will then select and transfer its interrupt-related responsibilities (i.e., handling the interrupt and determining the next interrupt-handing processor) to the processor which is executing the least important task. The selected processor will then be designated for handling interrupts unless and until it undergoes a task switch and selects a different processor.

Abstract: A debugger 100 is connected to a multi-processor system configured so that each processor autonomously accesses a shared memory and loads a program stored in the shared memory into storage of the processor. An identifier defined uniquely in the system is included in code of the program module in advance. A GUID detector 118 selects an ID-attached instruction, the identifier being described in a field of the instruction, from the memory image of the local memory of the processor to be inspected and extracts the identifier. A code retriever 120 selects code of a program module, corresponding to the extracted identifier, from a code holder 114. A memory layout output unit 122 outputs the code selected by the code retriever 120, while associating the code with a memory address of the module in the local memory.