Patents by Inventor Keisuke Izumi
Keisuke Izumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11532570Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.Type: GrantFiled: February 11, 2021Date of Patent: December 20, 2022Assignee: SANDISK TECHNOLOGIES LLCInventors: Genta Mizuno, Kenzo Iizuka, Satoshi Shimizu, Keisuke Izumi, Tatsuya Hinoue, Yujin Terasawa, Seiji Shimabukuro, Ryousuke Itou, Yanli Zhang, Johann Alsmeier, Yusuke Yoshida
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Publication number: 20220254733Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.Type: ApplicationFiled: February 11, 2021Publication date: August 11, 2022Inventors: Genta MIZUNO, Kenzo IIZUKA, Satoshi SHIMIZU, Keisuke IZUMI, Tatsuya HINOUE, Yujin TERASAWA, Seiji SHIMABUKURO, Ryousuke ITOU, Yanli ZHANG, Johann ALSMEIER, Yusuke YOSHIDA
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Patent number: 10593603Abstract: A chemical mechanical polishing apparatus includes a liquid filled bladder that exerts force on the back of the substrate being polished. The bladder can be a multi-chamber bladder having chambers filled with different ratios of hot and cold water. Eddy current detection during the polishing can be used to control the polishing process parameters.Type: GrantFiled: March 16, 2018Date of Patent: March 17, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Keisuke Izumi, Naomi Matsuda
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Publication number: 20190287866Abstract: A chemical mechanical polishing apparatus includes a liquid filled bladder that exerts force on the back of the substrate being polished. The bladder can be a multi-chamber bladder having chambers filled with different ratios of hot and cold water. Eddy current detection during the polishing can be used to control the polishing process parameters.Type: ApplicationFiled: March 16, 2018Publication date: September 19, 2019Inventors: Keisuke IZUMI, Naomi MATSUDA
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Patent number: 10381362Abstract: A three-dimensional memory device includes field effect transistors located on a substrate, lower metal interconnect structures embedded in first dielectric layers and located over the substrate, a source line located over the first dielectric layers, a stepped dielectric material portion located over the first dielectric layers and including stepped surfaces, an alternating stack of insulating layers and electrically conductive layers located over the source line and contacting the stepped surfaces of the stepped dielectric material portion, and memory stack structures extending through the alternating stack and including a memory film and a vertical semiconductor channel. A lateral extent of the stepped dielectric material portion decreases stepwise with a vertical distance from the substrate, and lateral extents of the electrically conductive layers increase with a vertical distance from the source line.Type: GrantFiled: May 15, 2018Date of Patent: August 13, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Zhixin Cui, Keisuke Izumi, Tomohiro Kubo
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Patent number: 10209636Abstract: Pattern-dependent random deviations in measurement of optimal focus distances can be minimized by separating scan paths into multiple types of scan paths that scan only a respective predetermined image region in semiconductor dies. A substrate including in-process semiconductor dies is coated with a photoresist layer, and is located onto a stage in a lithographic exposure tool. Maps of optimal focus distances are generated by performing optimal focus distance scans that cover a respective subset of image regions having distinct image patterns. The substrate can be leveled with respect to an optics system of the lithographic exposure tool employing a weighted average of multiple maps of optimal focus distances. Once the substrate is leveled on the stage, a lithographic exposure process can be performed with enhanced uniformity in the focus distances across the in-process semiconductor dies.Type: GrantFiled: March 7, 2018Date of Patent: February 19, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Tohru Toda, Keisuke Izumi, Michiaki Sano
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Patent number: 9691778Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.Type: GrantFiled: June 22, 2016Date of Patent: June 27, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Keisuke Izumi, Hiroaki Iuchi, Ryo Taura, Kentaro Sera, Akio Yanai
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Patent number: 9601502Abstract: A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. Electrically conductive via structures extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liners.Type: GrantFiled: July 15, 2016Date of Patent: March 21, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Michiaki Sano, Keisuke Izumi
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Patent number: 9524901Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of alternating sacrificial layers and insulating layers located over a major surface of a substrate. A contact mask having contact mask openings is provided over the stack, and a first over mask having first over mask openings is provided over the contact mask. A subset of the contact mask openings is substantially aligned with the first over mask openings. Contact openings are formed through the stack, wherein each of the contact openings extends substantially perpendicular to the major surface of the substrate to a respective one of the sacrificial layers. A plurality of electrically conductive via contacts is formed in the plurality of the contact openings.Type: GrantFiled: September 30, 2014Date of Patent: December 20, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Keisuke Izumi, Michiaki Sano, Hiroshi Sasaki
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Publication number: 20160322374Abstract: A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. Electrically conductive via structures extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liners.Type: ApplicationFiled: July 15, 2016Publication date: November 3, 2016Inventors: Michiaki SANO, Keisuke IZUMI
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Publication number: 20160307912Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.Type: ApplicationFiled: June 22, 2016Publication date: October 20, 2016Inventors: Keisuke Izumi, Hiroaki Iuchi, Ryo Taura, Kentaro Sera, Akio Yanai
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Patent number: 9412753Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of a plurality of alternating sacrificial layers and insulator layers located over a major surface of a substrate. A contact mask with at least one contact mask opening and at least one first terrace mask opening is provided over the stack, where the at least one first terrace mask opening is larger than the at least one contact mask opening. At least one first contact opening and at least one first terrace opening are simultaneously formed extending substantially perpendicular to the major surface of the substrate through the stack to a first sacrificial layer by etching a portion of the stack through the at least one contact mask opening and the at least one first terrace mask opening. A first electrically conductive via contact is deposited in the at least one first contact opening.Type: GrantFiled: September 30, 2014Date of Patent: August 9, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Keisuke Izumi, Michiaki Sano, Hiroshi Sasaki
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Patent number: 9401309Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.Type: GrantFiled: August 26, 2014Date of Patent: July 26, 2016Assignee: SANDISK TECHNOLOGIES LLCInventors: Keisuke Izumi, Naohito Yanagida, Michiaki Sano, Takehiro Yamazaki, Hiroaki Iuchi, Akio Yanai, Genta Mizuno, Minoru Yamaguchi
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Publication number: 20160093524Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of alternating sacrificial layers and insulating layers located over a major surface of a substrate. A contact mask having contact mask openings is provided over the stack, and a first over mask having first over mask openings is provided over the contact mask. A subset of the contact mask openings is substantially aligned with the first over mask openings. Contact openings are formed through the stack, wherein each of the contact openings extends substantially perpendicular to the major surface of the substrate to a respective one of the sacrificial layers. A plurality of electrically conductive via contacts is formed in the plurality of the contact openings.Type: ApplicationFiled: September 30, 2014Publication date: March 31, 2016Inventors: Keisuke Izumi, Michiaki Sano, Hiroshi Sasaki
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Publication number: 20160093626Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of a plurality of alternating sacrificial layers and insulator layers located over a major surface of a substrate. A contact mask with at least one contact mask opening and at least one first terrace mask opening is provided over the stack, where the at least one first terrace mask opening is larger than the at least one contact mask opening. At least one first contact opening and at least one first terrace opening are simultaneously formed extending substantially perpendicular to the major surface of the substrate through the stack to a first sacrificial layer by etching a portion of the stack through the at least one contact mask opening and the at least one first terrace mask opening. A first electrically conductive via contact is deposited in the at least one first contact opening.Type: ApplicationFiled: September 30, 2014Publication date: March 31, 2016Inventors: Keisuke Izumi, Michiaki Sano, Hiroshi Sasaki
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Publication number: 20160064281Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.Type: ApplicationFiled: August 26, 2014Publication date: March 3, 2016Inventors: Keisuke Izumi, Naohito Yanagida, Michiaki Sano, Takehiro Yamazaki, Hiroaki Iuchi, Akio Yanai, Genta Mizuno, Minoru Yamaguchi
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Patent number: 9236392Abstract: Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner.Type: GrantFiled: August 26, 2014Date of Patent: January 12, 2016Assignee: SANDISK TECHNOLOGIES INC.Inventors: Keisuke Izumi, Hiroaki Iuchi, Ryo Taura, Kentaro Sera, Akio Yanai
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Patent number: 7697784Abstract: There is provided a method of reducing block noise, mosquito noise and other image noises in an image by a filtering process using a smoothing filter, which block noise, mosquito noise and other image noises being caused at the time of decoding encoded, compressed image data on a block-by-block basis. The method includes changing the extent or intensity of the image noise reduction in the filtering process in a continuous or stepwise manner according to an output size or expansion rate of an image to be outputted to printer paper, photographic paper or other output media, thereby allowing the extent or intensity of the image noise reduction to be increased as the output size or expansion rate of the image increases. This method is capable of allowing the extent of the image noise reduction applied to image data to be perceived in a similar fashion, irrespective of the output size.Type: GrantFiled: November 14, 2005Date of Patent: April 13, 2010Assignee: Noritsu Koki Co., Ltd.Inventor: Keisuke Izumi
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Patent number: 7271932Abstract: Digital image processing apparatus is provided with a monitor for displaying an image, a moving picture reader for reading moving picture data, a memory for storing still image data obtained from the moving picture data, a display controller for displaying on the monitor a specified number of still image frames of the still image data, an image designator for allowing an operator to designate a still image frame for print among the specified number of still image frames, and an image outputter for outputting still image data corresponding to the designated still image frame as print data. The apparatus is further provided with an image converter for converting compressed moving picture data into still image data having a number of still image frames. Designation of a desired still image from moving picture data can be user-friendly performed.Type: GrantFiled: November 12, 2002Date of Patent: September 18, 2007Assignee: Noritsu Koki Co., Ltd.Inventor: Keisuke Izumi
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Publication number: 20060104538Abstract: There is provided a method of reducing block noise, mosquito noise and other image noises in an image by a filtering process using a smoothing filter, which block noise, mosquito noise and other image noises being caused at the time of decoding encoded, compressed image data on a block-by-block basis. The method includes changing the extent or intensity of the image noise reduction in the filtering process in a continuous or stepwise manner according to an output size or expansion rate of an image to be outputted to printer paper, photographic paper or other output media, thereby allowing the extent or intensity of the image noise reduction to be increased as the output size or expansion rate of the image increases. This method is capable of allowing the extent of the image noise reduction applied to image data to be perceived in a similar fashion, irrespective of the output size.Type: ApplicationFiled: November 14, 2005Publication date: May 18, 2006Applicant: Noritsu Koki Co., Ltd.Inventor: Keisuke Izumi