Abstract: A switching converter with improved load transient response is provided, including a panic comparator with a reset switch, a panic latch that is set by an output of the panic comparator and reset in conjunction with a strobe timing, and a timing generator which generates reset and strobe signals. The timing generator may include a gated oscillator, enabled by the panic latch. The panic comparator may include an HPF element, configured to accelerate the panic comparator response. The switching converter may be multi-phase.

Abstract: A switching converter with improved load transient response is provided, including a panic comparator with a reset switch, a panic latch that is set by an output of the panic comparator and reset in conjunction with a strobe timing, and a timing generator which generates reset and strobe signals. The timing generator may include a gated oscillator, enabled by the panic latch. The panic comparator may include an HPF element, configured to accelerate the panic comparator response. The switching converter may be multi-phase.

Abstract: A voltage proportional to a pulse width modulation (PWM) duty cycle is generated, using a low pass filter (LPF). A 2nd or higher order LPF is provided, giving a 90×(2n+1) degree phase shift for (n=0, 1, 2, . . . ), so that the sampling timing at the latter stages can be at the rising and/or falling edge of the PWM input signal. A switched capacitor circuit after the 2nd or higher order LPF is provided, removing a voltage ripple on an LPF output, and using a smaller device area.

Abstract: A semiconductor device includes a plurality of transistors, each having a gate electrode including extending portions having a length obtained by dividing the gate electrode causing interruption to switching at a desired frequency, wherein current inflow terminals of the plurality of transistors are connected to each other and current outflow terminals of the plurality of transistors are connected to each other.

Abstract: In a dead time adjusting circuit, a switch voltage appearing at a connection node between a first output switch and a second output switch, which are connected in series between two different potentials, is monitored to detect a first dead time, which is from a time at which the second output switch is turned off to a time at which the first output switch is turned on, and a second dead time, which is from a time at which the first output switch is turned off to a time at which the second output switch is turned on, each of the first and second dead times being feedback-controlled to be identical to a predetermined target value.

Abstract: A semiconductor device includes a plurality of transistors, each having a gate electrode including extending portions having a length obtained by dividing the gate electrode causing interruption to switching at a desired frequency, wherein current inflow terminals of the plurality of transistors are connected to each other and current outflow terminals of the plurality of transistors are connected to each other.

Abstract: In a dead time adjusting circuit, a switch voltage appearing at a connection node between a first output switch and a second output switch, which are connected in series between two different potentials, is monitored to detect a first dead time, which is from a time at which the second output switch is turned off to a time at which the first output switch is turned on, and a second dead time, which is from a time at which the first output switch is turned off to a time at which the second output switch is turned on, each of the first and second dead times being feedback-controlled to be identical to a predetermined target value.

Abstract: In a network relay router 10, a multicast routing protocol processing module 11A sequentially sends a join request message (CP1) to a router 30a functioning as a rendezvous point via an interface 101, based on the settings of a multicast group address or destination address and a sender VRF name. The network relay router 10 receives a multicast packet (DP1) from the router 30a via the interface 101 and acquires a sender address or source address of a transmission device SE from the received multicast packet. The network relay router 10 sends a join request message (CP2) via an interface 102 on the side of the transmission device SE and receives a multicast packet via the interface 102. This establishes an optimum multicast route (MR) between the transmission device SE and the network relay router 10.

Abstract: A multiphase DC/DC converter according to the present invention includes: a plurality of DC/DC converters whose outputs are connected in common to supply electric power to a load; a load state detection portion which detects a state of the load connected to the plurality of DC/DC converters and outputs a detection result; and a control circuit which drives each of the plurality of DC/DC converters based on outputs from the plurality of DC/DC converters, and based on an output from the load state detection portion, drives the plurality of DC/DC converters with output phases of the plurality of DC/DC converters deviated from each other or with the output phases of the plurality of DC/DC converters aligned with each other.

Abstract: In a network relay router 10, a multicast routing protocol processing module 11A sequentially sends a join request message (CP1) to a router 30a functioning as a rendezvous point via an interface 101, based on the settings of a multicast group address or destination address and a sender VRF name. The network relay router 10 receives a multicast packet (DP1) from the router 30a via the interface 101 and acquires a sender address or source address of a transmission device SE from the received multicast packet. The network relay router 10 sends a join request message (CP2) via an interface 102 on the side of the transmission device SE and receives a multicast packet via the interface 102. This establishes an optimum multicast route (MR) between the transmission device SE and the network relay router 10.

Abstract: A multiphase DC/DC converter according to the present invention includes: a plurality of DC/DC converters whose outputs are connected in common to supply electric power to a load; a load state detection portion which detects a state of the load connected to the plurality of DC/DC converters and outputs a detection result; and a control circuit which drives each of the plurality of DC/DC converters based on outputs from the plurality of DC/DC converters, and based on an output from the load state detection portion, drives the plurality of DC/DC converters with output phases of the plurality of DC/DC converters deviated from each other or with the output phases of the plurality of DC/DC converters aligned with each other.