Patents by Inventor Keisuke Kanamaru

Keisuke Kanamaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220009431
    Abstract: When an outlet is shut off, an ECU monitors whether a restoration condition for restoring the outlet is satisfied. When the restoration condition is not satisfied, the ECU shifts a process to return. When the restoration condition is satisfied, the ECU restores the outlet for which the restoration condition is satisfied. As the restoration condition, a condition that an external device connected to the outlet is removed with the outlet being shut off or a condition that the external device connected to the outlet is removed and then the external device is connected to the outlet with the outlet being shut off can be adopted.
    Type: Application
    Filed: June 16, 2021
    Publication date: January 13, 2022
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Keisuke KANAMARU
  • Publication number: 20210010561
    Abstract: An antivibration unit attachment structure according to the present aspect includes: a vibration absorption part having a first elastic member which is elastically deformable in a first direction and which is connected to a vibration generation part; and a second elastic member which supports the vibration absorption part and which is connected to a vibration reception part. The second elastic member includes a movable part that extends from the vibration absorption part to both sides in a second direction and that is supported by the vibration reception part. The second elastic member is elastically deformable in the first direction and has an elastic coefficient different from that of the first elastic member. The vibration reception part includes a regulation member that comes into contact with at least one of the vibration absorption part and the second elastic member and that limits displacement of the second elastic member to the first direction.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 14, 2021
    Inventors: Keisuke Kanamaru, Yasuhito Sato, Hiroyuki Asase, Masaaki Nishi
  • Patent number: 10696179
    Abstract: An electrically powered vehicle includes a power supply device, a first outlet, a second outlet, and an electronic control unit. The first outlet configured to be connected to an external equipment that is not constituent equipment of the electrically powered vehicle. The second outlet is configured to be connected to an external equipment that is not constituent equipment of the electrically powered vehicle. While first power feed and second power feed are being executed simultaneously, in a case where first power feed electric power exceeds a first threshold or in a case where total electric power of the first power feed and the second power feed exceeds a second threshold, the electronic control unit is configured to temporarily stop the second power feed and continue the first power feed.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: June 30, 2020
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Daisuke Ueo, Keisuke Kanamaru
  • Patent number: 10384543
    Abstract: An electrically powered vehicle includes a power supply device, a first outlet configured to be connectable to external equipment that is not constituent equipment of a vehicle, a second outlet configured to be connectable to external equipment that is not constituent equipment of the vehicle, a display device configured to display a first image representing that first power feed is in progress and a second image representing that second power feed is in progress, and an electronic control unit configured to control an image to be displayed on the display device. In a case where the first power feed and the second power feed are being executed, the electronic control unit is configured to perform control such that a display form of the first image is more noticeable than a display form of the second image.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: August 20, 2019
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Daisuke Ueo, Keisuke Kanamaru
  • Publication number: 20180118028
    Abstract: An electrically powered vehicle includes a power supply device, a first outlet configured to be connectable to external equipment that is not constituent equipment of a vehicle, a second outlet configured to be connectable to external equipment that is not constituent equipment of the vehicle, a display device configured to display a first image representing that first power feed is in progress and a second image representing that second power feed is in progress, and an electronic control unit configured to control an image to be displayed on the display device. In a case where the first power feed and the second power feed are being executed, the electronic control unit is configured to perform control such that a display form of the first image is more noticeable than a display form of the second image.
    Type: Application
    Filed: October 3, 2017
    Publication date: May 3, 2018
    Inventors: Daisuke Ueo, Keisuke Kanamaru
  • Publication number: 20180118037
    Abstract: An electrically powered vehicle includes a power supply device, a first outlet, a second outlet, and an electronic control unit. The first outlet configured to be connected to an external equipment that is not constituent equipment of the electrically powered vehicle. The second outlet is configured to be connected to an external equipment that is not constituent equipment of the electrically powered vehicle. While first power feed and second power feed are being executed simultaneously, a case where first power feed electric power exceeds a first threshold or in a case where total electric power of the first power feed and the second power feed exceeds a second threshold, the electronic control unit is configured to temporarily stop the second power feed and continue the first power feed.
    Type: Application
    Filed: October 13, 2017
    Publication date: May 3, 2018
    Inventors: Daisuke Ueo, Keisuke Kanamaru
  • Patent number: 8117578
    Abstract: There is provided a check target extraction unit that receives logic circuit information describing a logic circuit, and extracts at least one set of a start point register and an end point register from registers in the logic circuit, the start point register outputting an exception signal to be supplied to the end point register via the propagation control circuit, and a static hazard detection unit that determines whether, for the at least one set extracted by the check target extraction unit, there are a plurality of paths through which propagation of an exception signal from a start point register to an end point register is possible when the propagation control circuit, in response to a control signal, inhibits propagation of the exception signal.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: February 14, 2012
    Assignee: NEC Corporation
    Inventor: Keisuke Kanamaru
  • Patent number: 7774730
    Abstract: A method of designing a semiconductor integrated circuit by a computer, comprises: (A) reading an RTL data indicating RTL description of the semiconductor integrated circuit; and (B) providing a gating cell for clock gating during logic synthesis of the RTL description. The gating cell includes a latch circuit that latches an enable signal, which activates a target of the clock gating, in synchronization with a clock signal. The gating cell is provided separately from a timing exception path.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: August 10, 2010
    Assignee: NEC Corporation
    Inventor: Keisuke Kanamaru
  • Publication number: 20090172612
    Abstract: There is provided a check target extraction unit that receives logic circuit information describing a logic circuit, and extracts at least one set of a start point register and an end point register from registers in the logic circuit, the start point register outputting an exception signal to be supplied to the end point register via the propagation control circuit, and a static hazard detection unit that determines whether, for the at least one set extracted by the check target extraction unit, there are a plurality of paths through which propagation of an exception signal from a start point register to an end point register is possible when the propagation control circuit, in response to a control signal, inhibits propagation of the exception signal.
    Type: Application
    Filed: December 23, 2008
    Publication date: July 2, 2009
    Inventor: KEISUKE KANAMARU
  • Patent number: 7461326
    Abstract: The information processing method of the present invention detects redundant circuits as described below by means of an information processor that is provided with: a storage unit for storing circuit operation information that uses hardware description language and a library for performing a logic synthesis of the circuit operation information and converting to a net list; and a display unit. The information processor hierarchically arranges statement by statement the circuit operation information that is stored in the storage unit, and then refers to the library, performs a logic synthesis of the circuit operation information that has been hierarchically arranged and converts to a net list. The information processor then detects redundant fault sites, which are sites that are logically redundant from the net list, and displays information showing the redundant circuits that contain the redundant fault sites on the display unit.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: December 2, 2008
    Assignee: NEC Corporation
    Inventor: Keisuke Kanamaru
  • Publication number: 20080059938
    Abstract: A method of designing a semiconductor integrated circuit by a computer, comprises: (A) reading an RTL data indicating RTL description of the semiconductor integrated circuit; and (B) providing a gating cell for clock gating during logic synthesis of the RTL description. The gating cell includes a latch circuit that latches an enable signal, which activates a target of the clock gating, in synchronization with a clock signal. The gating cell is provided separately from a timing exception path.
    Type: Application
    Filed: August 29, 2007
    Publication date: March 6, 2008
    Applicant: NEC Corporation
    Inventor: Keisuke Kanamaru
  • Patent number: 7234127
    Abstract: An integrated circuit designing support apparatus includes a storage unit and a processing unit. The storage unit stores an RTL (Register Transfer Level) description with description of structurization for structurizing an RTL description model for an integrated circuit into modules, and a correspondence table which shows correspondence relation of each of output ports of a first module of the modules and a corresponding one of output ports of a second module of the modules.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: June 19, 2007
    Assignee: NEC Corporation
    Inventor: Keisuke Kanamaru
  • Patent number: 7028273
    Abstract: A delay optimization designing system and method is disclosed by which reduction of outputting delay and setup time of flip-flops and clock skew can be achieved and sufficient delay optimization can be achieved. A delay optimization designing system for a logic circuit includes a flip-flop selection section for selecting any flip-flop not to be substituted into a latch from within a given logic circuit, a flip-flop searching section for searching any flip-flop having a delay margin from among the flip-flops which are not selected by the flip-flop selection section, and a latch substitution section for substituting any flip-flop searched by the flip-flop searching section into a latch which passes a signal to the output side therethrough faster than the searched flip-flop.
    Type: Grant
    Filed: July 15, 2003
    Date of Patent: April 11, 2006
    Assignee: NEC Corporation
    Inventors: Keisuke Kanamaru, Ko Yoshikawa
  • Publication number: 20060010342
    Abstract: The information processing method of the present invention detects redundant circuits as described below by means of an information processor that is provided with: a storage unit for storing circuit operation information that uses hardware description language and a library for performing a logic synthesis of the circuit operation information and converting to a net list; and a display unit. The information processor hierarchically arranges statement by statement the circuit operation information that is stored in the storage unit, and then refers to the library, performs a logic synthesis of the circuit operation information that has been hierarchically arranged and converts to a net list. The information processor then detects redundant fault sites, which are sites that are logically redundant from the net list, and displays information showing the redundant circuits that contain the redundant fault sites on the display unit.
    Type: Application
    Filed: July 6, 2005
    Publication date: January 12, 2006
    Applicant: NEC Corporation
    Inventor: Keisuke Kanamaru
  • Publication number: 20050120324
    Abstract: An integrated circuit designing support apparatus includes a storage unit and a processing unit. The storage unit stores an RTL (Register Transfer Level) description with description of structurization for structurizing an RTL description model for an integrated circuit into modules, and a correspondence table which shows correspondence relation of each of output ports of a first module of the modules and a corresponding one of output ports of a second module of the modules.
    Type: Application
    Filed: December 2, 2004
    Publication date: June 2, 2005
    Inventor: Keisuke Kanamaru
  • Publication number: 20040015789
    Abstract: A delay optimization designing system and method is disclosed by which reduction of outputting delay and setup time of flip-flops and clock skew can be achieved and sufficient delay optimization can be achieved. A delay optimization designing system for a logic circuit includes a flip-flop selection section for selecting any flip-flop not to be substituted into a latch from within a given logic circuit, a flip-flop searching section for searching any flip-flop having a delay margin from among the flip-flops which are not selected by the flip-flop selection section, and a latch substitution section for substituting any flip-flop searched by the flip-flop searching section into a latch which passes a signal to the output side therethrough faster than the searched flip-flop.
    Type: Application
    Filed: July 15, 2003
    Publication date: January 22, 2004
    Applicant: NEC CORPORATION
    Inventors: Keisuke Kanamaru, Ko Yoshikawa