Patents by Inventor Keisuke Kaneko
Keisuke Kaneko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150210595Abstract: A filler for construction includes a hardening material, a fine powder as an admixture material, and sludge water obtained by separating sand and gravel from discharged water provided by washing concrete handling equipment.Type: ApplicationFiled: August 5, 2013Publication date: July 30, 2015Inventors: Yoshinori Iida, Keisuke Kaneko
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Publication number: 20130316256Abstract: This fuel cell system monitors the temperature of an off-gas combusting unit detected by a combustor temperature detecting unit in a constant output operation state such as a rated operation state where a sweeping current of a cell stack becomes constant, rather than directly measuring the fuel property, and controls the flow rate of the cathode gas so that the temperature of the off-gas combusting unit reaches a target temperature. Moreover, the fuel cell system determines the fuel property based on the variation of the flow rate of the cathode gas changed until the temperature of the off-gas combusting unit reaches the target temperature and the temperature of the cathode gas. Thus, it is possible to simplify the configuration required for determining whether the fuel property has changed or not as compared to a conventional method of measuring a plurality of factors of the fuel property.Type: ApplicationFiled: December 27, 2011Publication date: November 28, 2013Applicant: JX NIPPON OIL & ENERGY CORPORATIONInventors: Keisuke Kaneko, Takeshi Ibuka
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Patent number: 7970998Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.Type: GrantFiled: March 17, 2006Date of Patent: June 28, 2011Assignee: Panasonic CorporationInventors: Takao Yamamoto, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko, Hazuki Okabayashi
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Patent number: 7953935Abstract: A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.Type: GrantFiled: February 8, 2006Date of Patent: May 31, 2011Assignee: Panasonic CorporationInventors: Hazuki Okabayashi, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko
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Patent number: 7636812Abstract: An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps 2-1 and 2-2), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step 2-6). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step 2-3), or a second hit/miss determination is performed by accessing all the ways (Step 2-4).Type: GrantFiled: March 22, 2006Date of Patent: December 22, 2009Assignee: Panasonic CorporationInventor: Keisuke Kaneko
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Publication number: 20090235028Abstract: An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps 2-1 and 2-2), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step 2-6). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step 2-3), or a second hit/miss determination is performed by accessing all the ways (Step 2-4).Type: ApplicationFiled: March 22, 2006Publication date: September 17, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventor: Keisuke Kaneko
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Publication number: 20090100231Abstract: A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.Type: ApplicationFiled: February 8, 2006Publication date: April 16, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hazuki Okabayashi, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko
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Publication number: 20090094474Abstract: An information processing device controls an access unit which accesses a memory corresponding to an address space where an address belongs, the address being generated using at least two pieces of address generation source information.Type: ApplicationFiled: December 26, 2005Publication date: April 9, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Keisuke Kaneko, Masaitsu Nakajima, Takanobu Tani
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Publication number: 20090077318Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.Type: ApplicationFiled: March 17, 2006Publication date: March 19, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Takao Yamamoto, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko, Hazuki Okabayashi
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Patent number: 7502887Abstract: The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.Type: GrantFiled: September 8, 2004Date of Patent: March 10, 2009Assignee: Panasonic CorporationInventors: Tetsuya Tanaka, Hazuki Okabayashi, Ryuta Nakanishi, Tokuzo Kiyohara, Takao Yamamoto, Keisuke Kaneko
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Publication number: 20080270658Abstract: Provided is a simply structured multiprocessor system which equally distributes access performance for accessing a shared memory among plural master units accessing the shared memory. The multiprocessor system includes plural master units PU0 and PU1 each of which issues an access request for accessing the shared memory, a bus IF unit 4-10 which accesses a bus by a split transaction scheme and separately executes a request phase for accepting the access request; and a transfer phase for executing data transfer in response to the accepted access request. In the case where one of the master units consecutively issues plural access requests without an interval of a predetermined time period, the bus IF unit 4-10 restricts the number of consecutive transfer phase executions corresponding to the plural access requests to be not more than N.Type: ApplicationFiled: April 24, 2008Publication date: October 30, 2008Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Keisuke KANEKO, Takao YAMAMOTO, Masayuki YAMASAKI, Nobuo HIGAKI, Kazushi KURATA, Ryuta NAKANISHI
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Patent number: 7000135Abstract: In an information processing device including a processing circuit that performs processing in synchronization with a clock, and a clock supply control circuit that controls supply of the clock to the processing circuit, the number of cycles required from start of execution of processing in the processing circuit until output of a result of the processing is extracted, the extracted number of cycles is transferred to the clock supply control circuit, the supply of the clock is started when the processing is started in the processing circuit, and the supply of the clock to the processing circuit is stopped when the supply of the clock with the number of cycles is completed. Thus, a clock control method and an information processing device employing the clock control method are provided that allow power consumption to be reduced without impairing an execution efficiency of pipeline processing.Type: GrantFiled: March 8, 2002Date of Patent: February 14, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Keisuke Kaneko
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Publication number: 20020129292Abstract: In an information processing device including a processing circuit that performs processing in synchronization with a clock, and a clock supply control circuit that controls supply of the clock to the processing circuit, the number of cycles required from start of execution of processing in the processing circuit until output of a result of the processing is extracted, the extracted number of cycles is transferred to the clock supply control circuit, the supply of the clock is started when the processing is started in the processing circuit, and the supply of the clock to the processing circuit is stopped when the supply of the clock with the number of cycles is completed. Thus, a clock control method and an information processing device employing the clock control method are provided that allow power consumption to be reduced without impairing an execution efficiency of pipeline processing.Type: ApplicationFiled: March 8, 2002Publication date: September 12, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Keisuke Kaneko
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Patent number: 6161171Abstract: A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit.Type: GrantFiled: June 26, 1998Date of Patent: December 12, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Toru Morikawa, Nobuo Higaki, Shinji Ozaki, Keisuke Kaneko, Satoshi Ogura, Masato Suzuki