Abstract: It is determined that indoor condensation of hydrogen peroxide vapor is to occur, if there is a solution with which both (Equation 1): PT·y1=P01·x1·?1 and (Equation 2): PT·y2=P02·x2·?2 hold. With this, it is possible to accurately determine whether indoor condensation of hydrogen peroxide vapor is to occur or not in decontamination.

Abstract: An electronic component module includes a board, a plurality of external terminals provided on a first surface of the board, and a first semiconductor chip provided on a region on the first surface surrounded by the plurality of external terminals. The first semiconductor chip protrudes more along a normal to the first surface than ends of the external terminals do.

Abstract: An electronic component module includes a board, a plurality of external terminals provided on a first surface of the board, and a first semiconductor chip provided on a region on the first surface surrounded by the plurality of external terminals. The first semiconductor chip more protrudes along a normal to the first surface than ends of the external terminals do.

Abstract: It is determined that indoor condensation of hydrogen peroxide vapor is to occur, if there is a solution with which both (Equation 1): PT·y1=P01·x1·?1 and (Equation 2): PT·y2=P02·x2·?2 hold. With this, it is possible to accurately determine whether indoor condensation of hydrogen peroxide vapor is to occur or not in decontamination.

Abstract: A semiconductor device includes an insulating film formed on a substrate; an interconnect layer including a plurality of interconnects formed in the insulating film; and a pad formed on the insulating film. In a region containing at least a part of a section below the pad, a narrow spacing region is formed, where a spacing between the adjacent interconnects is shorter than that in a section outside the region containing at least a part of the section below the pad.

Abstract: A semiconductor device includes an insulating film formed on a substrate; an interconnect layer including a plurality of interconnects formed in the insulating film; and a pad formed on the insulating film. In a region containing at least a part of a section below the pad, a narrow spacing region is formed, where a spacing between the adjacent interconnects is shorter than that in a section outside the region containing at least a part of the section below the pad.

Abstract: In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a reference input/output terminal, further delayed in a second delay addition circuit, and then inputted to the second logic circuit. By varying respective amounts of delay added by the first and second delay addition circuits from each other, AC timing specifications are satisfied and it is determined whether or not the semiconductor integrated circuit has passed a test based on whether or not the output of the second logic circuits is a desired signal relative to the input of the first logic circuit.

Abstract: In a calculator 520, a test bench 521 for event-driven asynchronous simulation described in an HDL is stored. An input-related description portion in the test bench 521 is input to an LSI tester 510 and converted into a signal input to a DUT 500, and then the signal input is applied to the DUT 500. Thereafter, an output signal produced from the DUT in response to the signal input is input to the LSI tester 510 and compared with an output signal obtained from a voltage condition table and the like, thereby determining the level of the output signal. This comparison result is input to the calculator 520, in which the comparison result is compared with an expected value and output waveform data described in the HDL test bench 521, so as to make a pass/failure determination for the DUT 500. It is thus possible to test the LSI (DUT) under the same conditions as the LSI is actually used in a product.

Abstract: In a semiconductor integrated circuit, one of two signals generated from a first logic circuit is delayed in a first delay addition circuit, looped back by an input/output terminal, and then inputted to a second logic circuit. The other output of the first logic circuit is looped back by a reference input/output terminal, further delayed in a second delay addition circuit, and then inputted to the second logic circuit. By varying respective amounts of delay added by the first and second delay addition circuits from each other, AC timing specifications are satisfied and it is determined whether or not the semiconductor integrated circuit has passed a test based on whether or not the output of the second logic circuits is a desired signal relative to the input of the first logic circuit.