Abstract: A solid-state image sensing device reads repeatedly M times an analog signal having a black level, during a first A/D conversion period. A frequency divider frequency-divides by M a pulse train depending on the analog signal having a black level that is read repeatedly M times, and a counter circuit counts the pulses of the pulse train, which is frequency-divided by M. Thereafter, the solid-state image sensing device reads repeatedly N times an analog signal having a signal level, during a second A/D conversion period. The frequency divider frequency-divides by N a pulse train depending on the analog signal having a signal level that is read repeatedly N times, and the counter circuit counts the pulses of the pulse train, which is frequency-divided by N. M and N satisfy the relationship N?M.

Abstract: A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.

Abstract: An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits to perform arithmetic processing based on input analog signals, a capacitor to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits, an analog-to-digital (A/D) conversion circuit to convert the charge amount stored in the capacitor to digital data, and a digital arithmetic circuit to calculate a cumulative value based on the converted digital data.

Abstract: An arithmetic circuit to calculate a cumulative value of results of parallel arithmetic processing, in which the increase of the circuit area for multiple-term arithmetic computation and the degradation of accuracy of holding of computation results in a short time can be prevented. The arithmetic circuit has plural analog arithmetic circuits (1) to perform arithmetic processing based on input analog signals, a capacitor (2) to hold a charge amount proportional to a total sum of results of computations by the plural analog arithmetic circuits (1), an A/D conversion circuit (3) to convert the charge amount stored in the capacitor (2) to digital data, and a digital arithmetic circuit (4) to calculate a cumulative value based on the converted digital data.

Abstract: A product-sum operation circuit includes a sorting block (4) which outputs a plurality of operand values x1, x2, . . . xi in descending or ascending order of magnitude, and an operation unit (1) which multiplies each operand value xi output from the sorting block (4) by a corresponding operand value Wi and calculates the accumulated sum of multiplication results.