Patents by Inventor Keisuke Nadamoto

Keisuke Nadamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140265094
    Abstract: For providing a die bonder, a bonding head device and a collet position adjusting method for enabling an automatic correction (adjustment) of errors, including height and inclination thereof, when exchanging a collet, with a simple structure thereof, in the bonding head device, having a holder 41h for guiding a vacuum for suction in an inside thereof, a shank 41s and a collet 41c, detachably attached at a tip of the holder, for adjusting the position of the collet after exchange of the collet, a reverse-side surface of that collet is photographed, before exchanging it, by a reverse-side surface photographing camera 42, which is disposed below the bonding head device, and after the exchange of the collet, the reverse-side surface of that collet exchanged, and then correction is made on positions of the collets, so that pictures photographed before/after the exchange thereof come to be coincident with.
    Type: Application
    Filed: September 12, 2013
    Publication date: September 18, 2014
    Applicant: HITACHI HIGH-TECH INSTRUMENTS CO., LTD.
    Inventors: Hideharu KOBASHI, Keisuke NADAMOTO, Yoshihisa NAKAJIMA
  • Patent number: 8703583
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: April 22, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroshi Maki, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo
  • Publication number: 20100055878
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Application
    Filed: November 13, 2009
    Publication date: March 4, 2010
    Inventors: Hiroshi MAKI, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo
  • Patent number: 7629231
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: December 8, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Maki, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo
  • Publication number: 20070275544
    Abstract: A technique with which die bonding can be carried out without forming a void in a bond area is provided. A vacuum supply line that connects to a vacuum chuck hole formed in the bottom face of a vacuuming collet and supplies the vacuuming collet with reduced pressure for vacuum chucking a chip is constructed of two systems. That is, the vacuum supply line is so structured that a first pipe and a second pipe connect to the vacuuming collet. The first pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is unstuck from a dicing tape and transported to a mounting position on a wiring substrate. The second pipe supplies the vacuuming collet with a vacuum that provides suction force when a chip is mounted over a wiring substrate. The intensity of the vacuum (suction force) supplied to the vacuuming collet is controlled by opening or closing valves respectively installed in the pipes.
    Type: Application
    Filed: April 16, 2007
    Publication date: November 29, 2007
    Inventors: Hiroshi Maki, Masayuki Mochizuki, Ryuichi Takano, Yoshiaki Makita, Haruhiko Fukasawa, Keisuke Nadamoto, Tatsuyuki Okubo
  • Patent number: 6898848
    Abstract: A chip is fixed via an insulating film on a tape carrier on one main surface of which plural inner leads are laid and each electrode pad of the chip is bonded to each inner lead. The inner lead is bonded to the electrode pad when the chip is supplied in a fixed position for a bonding tool using a sprocket hole of the ape carrier. Next, the respective positions of the inner lead and the electrode pad are recognized and the center line of the inner lead is recognized. The inner lead is touched to the chip by the bonding tool and after the inner lead is pushed in the direction of the base and bent in the form of a letter S. the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: May 31, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Tatsuyuki Ohkubo, Keisuke Nadamoto, Yoshifumi Katayama
  • Publication number: 20030084563
    Abstract: To stabilize the form of a letter S of an inner lead after bonding in a method of manufacturing &mgr;BGA·IC in which a chip is fixed via an insulating film on a tape carrier on one main surface of which plural inner leads are laid and each electrode pad of the chip is bonded to each inner lead, when the inner lead is bonded to the electrode pad, first, the chip is supplied in a fixed position for a bonding tool using a sprocket hole of the tape carrier. Next, the respective positions of the inner lead and the electrode pad are recognized using a feature lead and an electrode pad. Afterward, the center line of the inner lead is recognized, the inner lead is touched to the chip by the bonding tool and after the inner lead is pushed in the direction of the base and bent in the form of a letter S, the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.
    Type: Application
    Filed: December 13, 2002
    Publication date: May 8, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Tatsuyuki Ohkubo, Keisuke Nadamoto, Yoshifumi Katayama
  • Patent number: 6516515
    Abstract: A method for stabilizing the form of a letter S of an inner lead after bonding in a method of manufacturing &mgr;BGA·IC in which a chip is fixed via an insulating film on a tape carrier on one main surface of which plural inner leads are laid and each electrode pad of the chip is bonded to each inner lead is disclosed. The inner lead is bonded to the electrode pad when the chip is supplied in a fixed position for a bonding tool. Next, the respective positions of the inner lead and the electrode pad are recognized using a feature lead and an electrode pad. The center line of the inner lead is recognized, the inner lead is pushed to the chip in the direction of the base and bent in the form of a letter S, the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.
    Type: Grant
    Filed: June 7, 2001
    Date of Patent: February 11, 2003
    Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Tatsuyuki Ohkubo, Keisuke Nadamoto, Yoshifumi Katayama
  • Publication number: 20010027606
    Abstract: To stabilize the form of a letter S of an inner lead after bonding in a method of manufacturing &mgr;BGA•IC in which a chip is fixed via an insulating film on a tape carrier on one main surface of which plural inner leads are laid and each electrode pad of the chip is bonded to each inner lead, when the inner lead is bonded to the electrode pad, first, the chip is supplied in a fixed position for a bonding tool using a sprocket hole of the tape carrier. Next, the respective positions of the inner lead and the electrode pad are recognized using a feature lead and an electrode pad. Afterward, the center line of the inner lead is recognized, the inner lead is touched to the chip by the bonding tool and after the inner lead is pushed in the direction of the base and bent in the form of a letter S, the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.
    Type: Application
    Filed: June 7, 2001
    Publication date: October 11, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Tatsuyuki Ohkubo, Keisuke Nadamoto, Yoshifumi Katayama
  • Patent number: 6279226
    Abstract: A method and apparatus for stabilizing the form of a letter S of an inner lead after bonding in a method of manufacturing &mgr;BGAoIC in which a chip is fixed via an insulating film on a tape carrier on one main surface of which plural inner leads are laid and each electrode pad of the chip is bonded to each inner lead is disclosed. The inner lead is bonded to the electrode pad when the chip is supplied in a fixed position for a bonding tool using a sprocket hole of the tape carrier. Next, the respective positions of the inner lead and the electrode pad are recognized using a feature lead and an electrode pad. Afterward, the center line of the inner lead is recognized, the inner lead is touched to the chip by the bonding tool and after the inner lead is pushed in the direction of the base and bent in the form of a letter S, the end of the inner lead is bonded to the electrode pad by thermocompression by the bonding tool.
    Type: Grant
    Filed: January 6, 1998
    Date of Patent: August 28, 2001
    Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics Co., Ltd.
    Inventors: Tatsuyuki Ohkubo, Keisuke Nadamoto, Yoshifumi Katayama