Patents by Inventor Keisuke Nakazono

Keisuke Nakazono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11468539
    Abstract: An image processing device includes a plurality of processing units which are connected to a common data bus and performing predetermined processing on data read from a data storage unit connected to the data bus via the data bus. At least one of the processing units includes: a plurality of processing modules that are configured to perform predetermined processing on input data; an input/output module that is configured to operate as the processing module that directly inputs and outputs data from/to outside without passing through the data bus; and a connection switching unit that is configured to change a configuration of a pipeline by switching a connection between the processing modules according to input settings, and is an image processing unit that are configured to perform a pipeline processing by each of the processing modules constituting the pipeline.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: October 11, 2022
    Assignee: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Akira Ueno
  • Publication number: 20200143508
    Abstract: An image processing device includes a plurality of processing units which are connected to a common data bus and performing predetermined processing on data read from a data storage unit connected to the data bus via the data bus. At least one of the processing units includes: a plurality of processing modules that are configured to perform predetermined processing on input data; an input/output module that is configured to operate as the processing module that directly inputs and outputs data from/to outside without passing through the data bus; and a connection switching unit that is configured to change a configuration of a pipeline by switching a connection between the processing modules according to input settings, and is an image processing unit that are configured to perform a pipeline processing by each of the processing modules constituting the pipeline.
    Type: Application
    Filed: January 3, 2020
    Publication date: May 7, 2020
    Applicant: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Akira Ueno
  • Patent number: 10633730
    Abstract: Provided is a material for a cold-rolled stainless steel sheet having a chemical composition containing, by mass %, C: 0.01% to 0.05%, Si: 0.02% to 0.75%, Mn: 0.1% to 1.0%, P: 0.04% or less, S: 0.01% or less, Cr: 16.0% to 18.0%, Al: 0.001% to 0.10%, N: 0.01% to 0.06% and the balance being Fe and inevitable impurities. The material has a metallographic structure including a martensite phase having an area ratio of 5% to 50% and the balance being a ferrite phase. A ferrite phase in portions extending from surface layers of front and back surfaces of a steel sheet has an average grain diameter of 20 ?m or more and 50 ?m or less, and a ferrite phase in a central portion of the sheet includes an unrecrystallized ferrite phase.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: April 28, 2020
    Assignee: JFE Steel Corporation
    Inventors: Ayako Ta, Yukihiro Matsubara, Yukio Kimura, Masataka Yoshino, Keisuke Nakazono, Sumio Kaiho, Saiichi Murata, Nobukazu Kitagawa
  • Patent number: 10550454
    Abstract: Provided is a cold-rolled ferritic stainless steel sheet having a chemical composition that contains, by mass %, C: 0.01% or more and 0.05% or less, Si: 0.02% or more and 0.75% or less, Mn: 0.1% or more and 1.0% or less, P: 0.04% or less, S: 0.01% or less, Al: 0.001% or more and 0.10% or less, N: 0.01% or more and 0.06% or less, Cr: 16.0% or more and 18.0% or less, and the balance being Fe and inevitable impurities. The metallographic structure includes a ferrite phase, in which the average grain diameter is 10 ?m or less, in which the proportion of ferrite grains having a grain diameter of 10 ?m or more and less than 40 ?m is 60% or more, and in which the proportion of ferrite grains having a grain diameter of less than 5 ?m is less than 20%.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: February 4, 2020
    Assignee: JFE Steel Corporation
    Inventors: Ayako Ta, Yukihiro Matsubara, Yukio Kimura, Keisuke Nakazono, Masataka Yoshino
  • Publication number: 20200005425
    Abstract: An image processing device includes a plurality of processing units which are connected to a common data bus and performing predetermined processing on data read from a data storage unit connected to the data bus via the data bus. At least one of the processing units includes: a plurality of processing modules that perform predetermined processing on input data; an input/output module that operates as the processing module that directly inputs and outputs data from/to outside without passing through the data bus; and a connection switching unit that changes a configuration of a pipeline by switching a connection between the processing modules according to input settings, and is an image processing unit that performs a pipeline processing by each of the processing modules constituting the pipeline.
    Type: Application
    Filed: September 12, 2019
    Publication date: January 2, 2020
    Applicant: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Akira Ueno
  • Patent number: 10453166
    Abstract: There is provided an image processing device includes an image processing section including a pipeline in which a plurality of processing modules is connected in series, and a system control section performing setting the pipeline processing to be performed by the image processing section. Each of the processing modules includes a data buffer temporarily store the data, on arithmetic section configured to perform an arithmetic operation of the process according to a setting of processing content by the system control section, and a control section configured to select a data transfer path within the processing module and control an operation of the data buffer according to a setting of a data transfer path by the system control section. The image processing section further includes a connection switching section configured to switch a connection between the processing modules according to a setting of a pipeline configuration by the system control section.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 22, 2019
    Assignee: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Akira Ueno
  • Patent number: 10241721
    Abstract: There is provided an image processing device include an image processing section including a pipeline in which a plurality of processing modules is connected in series, each processing modules being configured to perform a predetermined process on input data, and the image processing section performing pipeline processing by the processing modules sequentially performing the process. Each of the processing modules includes a data buffer configured to temporarily store the data in unit of processing, and a control section configured to determine whether or not to store the data in the data buffer on the basis of a state of a data flow in the pipeline processing and a state of the data stored in the data buffer, and to select a path within the processing module by which the data is transferred on the basis of a determination result, and to control an operation of the data buffer.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: March 26, 2019
    Assignee: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Akira Ueno
  • Publication number: 20190079881
    Abstract: The present invention provides a plurality of bus masters configured to output an access request to a memory in which an address space is divided into a plurality of banks, an arbiter configured to arbitrate the access request output from each of the bus masters and control access to the memory in response to the access request which has been accepted, and a request acceptance history acquisition section configured to acquire information about a plurality of access requests accepted by the arbiter and output the stored request acceptance history information. At least one bus master with a high priority is configured to output the access request for specifying the banks in a determined order with reference to the request acceptance history information when the plurality of banks of the memory are successively accessed.
    Type: Application
    Filed: November 14, 2018
    Publication date: March 14, 2019
    Applicant: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Akira Ueno
  • Publication number: 20180365796
    Abstract: There is provided an image processing device in which an image processing section of a pipeline configuration in which a plurality of processing modules for performing predetermined processing on input data are connected in series performs image processing on data read from a data storage section via a data bus. The image processing section includes an input/output module incorporated into the pipeline as a processing module configured to perform processing different from the processing to be performed by each of the processing modules. The input/output module performs data transmission from and to an external processing section outside the image processing section via an external interface section without involving the data bus at a position where the input/output module is incorporated into the pipeline and the external interface section converts a format of pixel data to be transmitted by the input/output module.
    Type: Application
    Filed: August 23, 2018
    Publication date: December 20, 2018
    Applicant: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Akira Ueno
  • Publication number: 20180074752
    Abstract: There is provided an image processing device include an image processing section including a pipeline in which a plurality of processing modules is connected in series, each processing modules being configured to perform a predetermined process on input data, and the image processing section performing pipeline processing by the processing modules sequentially performing the process. Each of the processing modules includes a data buffer configured to temporarily store the data in unit of processing, and a control section configured to determine whether or not to store the data in the data buffer on the basis of a state of a data flow in the pipeline processing and a state of the data stored in the data buffer, and to select a path within the processing module by which the data is transferred on the basis of a determination result, and to control an operation of the data buffer.
    Type: Application
    Filed: November 15, 2017
    Publication date: March 15, 2018
    Applicant: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Akira Ueno
  • Publication number: 20180068413
    Abstract: There is provided an image processing device includes an image processing section including a pipeline in which a plurality of processing modules is connected in series, and a system control section performing setting the pipeline processing to be performed by the image processing section. Each of the processing modules includes a data buffer temporarily store the data, on arithmetic section configured to perform an arithmetic operation of the process according to a setting of processing content by the system control section, and a control section configured to select a data transfer path within the processing module and control an operation of the data buffer according to a setting of a data transfer path by the system control section. The image processing section further includes a connection switching section configured to switch a connection between the processing modules according to a setting of a pipeline configuration by the system control section.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 8, 2018
    Applicant: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Akira Ueno
  • Publication number: 20170283923
    Abstract: Provided is a cold-rolled ferritic stainless steel sheet having a chemical composition that contains, by mass %, C: 0.01% or more and 0.05% or less, Si: 0.02% or more and 0.75% or less, Mn: 0.1% or more and 1.0% or less, P: 0.04% or less, S: 0.01% or less, Al: 0.001% or more and 0.10% or less, N: 0.01% or more and 0.06% or less, Cr: 16.0% or more and 18.0% or less, and the balance being Fe and inevitable impurities. The metallographic structure includes a ferrite phase, in which the average grain diameter is 10 ?m or less, in which the proportion of ferrite grains having a grain diameter of 10 ?m or more and less than 40 ?m is 60% or more, and in which the proportion of ferrite grains having a grain diameter of less than 5 ?m is less than 20%.
    Type: Application
    Filed: July 2, 2015
    Publication date: October 5, 2017
    Applicant: JFE STEEL CORPORATION
    Inventors: Ayako Ta, Yukihiro Matsubara, Yukio Kimura, Keisuke Nakazono, Masataka Yoshino
  • Publication number: 20170275744
    Abstract: Provided is a material for a cold-rolled stainless steel sheet having a chemical composition containing, by mass %, C: 0.01% to 0.05%, Si: 0.02% to 0.75%, Mn: 0.1% to 1.0%, P: 0.04% or less, S: 0.01% or less, Cr: 16.0% to 18.0%, Al: 0.001% to 0.10%, N: 0.01% to 0.06% and the balance being Fe and inevitable impurities. The material has a metallographic structure including a martensite phase having an area ratio of 5% to 50% and the balance being a ferrite phase. A ferrite phase in portions extending from surface layers of front and back surfaces of a steel sheet has an average grain diameter of 20 ?m or more and 50 ?m or less, and a ferrite phase in a central portion of the sheet includes an unrecrystallized ferrite phase.
    Type: Application
    Filed: July 2, 2015
    Publication date: September 28, 2017
    Applicant: JFE STEEL CORPORATION
    Inventors: Ayako Ta, Yukihiro Matsubara, Yukio Kimura, Masataka Yoshino, Keisuke Nakazono, Sumio Kaiho, Saiichi Murata, Nobukazu Kitagawa
  • Patent number: 9609215
    Abstract: A moving-image recording/reproduction apparatus includes a first image processing apparatus configured to divide a region of an image signal into first and second regions when the image signal of each frame in a high-resolution moving image is input and generate first moving-image data by performing moving-image processing on the image signal of the first region and a second image processing apparatus configured to generate second moving-image data by performing the moving-image processing on the image signal of the second region.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: March 28, 2017
    Assignee: OLYMPUS CORPORATION
    Inventor: Keisuke Nakazono
  • Patent number: 9531988
    Abstract: An image output apparatus includes a first synthesis processing unit configured to generate a first synthetic image for display through a synthesis process and output the first synthetic image, a second synthesis processing unit configured to generate a second synthetic image for synthesis through a synthesis process and cause the second synthetic image to be stored in the external storage area, and an image selection control unit configured to instruct the second synthesis processing unit to generate the second synthetic image, select whether or not the second synthetic image is to be used as one of the input images used to generate the first synthetic image, and instruct the first synthesis processing unit to generate the first synthetic image including the plurality of selected input images.
    Type: Grant
    Filed: October 13, 2014
    Date of Patent: December 27, 2016
    Assignee: OLYMPUS CORPORATION
    Inventors: Ryusuke Tsuchida, Keisuke Nakazono, Akira Ueno
  • Patent number: 9363440
    Abstract: An imaging device includes an imaging unit which outputs captured image data corresponding to a pixel signal, a plurality of image processing units which generate any one of first image data being performed first image processing on the captured image data and second image data being performed second image processing on the captured image data, a display processing unit which causes an image corresponding to the second image data to be displayed on a display device which displays an image corresponding to image data input at a predetermined timing of a second synchronization signal, and a control unit which changes a setting of a phase difference between the first synchronization signal and the second synchronization signal and switches between the first image processing and the second image processing to be executed by each of the plurality of image processing units.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: June 7, 2016
    Assignee: OLYMPUS CORPORATION
    Inventors: Keisuke Nakazono, Hideru Ikeda, Akira Ueno
  • Patent number: 9264609
    Abstract: An image processing apparatus includes: an image processing section that receives input images of a plurality of frames, divides an image of each input frame into a plurality of blocks for each image of the frame, and generates an image corresponding to each frame by performing predetermined image processing on each division block; and an overlap width control section that separately saves overlap width data to be used in each of a plurality of image processing operations by the image processing section for generating the image corresponding to each frame for each piece of the overlap width data corresponding to each image processing operation when image data included in an overlap width area in which block areas overlap within the image of each frame is saved as overlap width data, and switches the overlap width data to be used when the image processing section performs each image processing operation.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: February 16, 2016
    Assignee: OLYMPUS CORPORATION
    Inventors: Tomonori Yonemoto, Hideru Ikeda, Keisuke Nakazono, Akira Ueno
  • Publication number: 20150365597
    Abstract: A moving-image recording/reproduction apparatus includes a first image processing apparatus configured to divide a region of an image signal into first and second regions when the image signal of each frame in a high-resolution moving image is input and generate first moving-image data by performing moving-image processing on the image signal of the first region and a second image processing apparatus configured to generate second moving-image data by performing the moving-image processing on the image signal of the second region.
    Type: Application
    Filed: June 2, 2015
    Publication date: December 17, 2015
    Applicant: OLYMPUS CORPORATION
    Inventor: Keisuke Nakazono
  • Patent number: 9070201
    Abstract: An image processing apparatus includes a buffer unit which stores image data of one input image, an input control unit which causes the buffer unit to store the image data of the input image, a processing operation unit which outputs image data of a processed image generated by performing image processing based on one of a plurality of set processing conditions, a plurality of output control units corresponding to the processing conditions, wherein each output control unit causes the image data necessary when image processing is performed in a corresponding processing condition to be output from the buffer unit to the processing operation unit and causes the image data of the processed image to be output to a subsequent-stage processing circuit, and an output arbitrating unit which determines which processing condition is used to perform the image processing and permits the corresponding output control unit to perform output control.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: June 30, 2015
    Assignee: OLYMPUS CORPORATION
    Inventors: Ryusuke Tsuchida, Akira Ueno, Keisuke Nakazono
  • Patent number: 9026697
    Abstract: A data processing apparatus may include a data acquisition unit, a buffer unit that includes a plurality of division buffers, a valid data area determination unit that calculates an area of valid data, a buffer state management unit that manages whether or not the data is stored in the division buffer, a data write control unit that writes data of a unit of the storage capacity of the division buffer, which at least includes data indicated to be valid data by the valid data information within the data, to the division buffer in which no data is stored, the division buffer being selected based on the management information, and a data read control unit that reads data indicated to be valid data by the valid data information from the division buffer in which data is stored, the division buffer being selected based on the management information.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: May 5, 2015
    Assignee: Olympus Corporation
    Inventors: Tomonori Yonemoto, Hideru Ikeda, Keisuke Nakazono