Abstract: In a control device for an internal combustion engine, which includes control unit that has a processor with a plurality of cores and that computes various tasks associated with operation of the internal combustion engine, the control unit includes a selecting unit, that selects at least one core used in the computation from among the plurality of cores, a computing unit that distributes the tasks to the at least one core selected by the selecting unit to perform computation, and an acquisition unit that acquires an engine, rotational speed of the internal combustion engine, and, when the engine rotational speed acquired by the acquisition unit is higher than or equal to a predetermined threshold, the selecting unit increases the number of the cores selected as compared with when the acquired engine rotational speed is lower than the predetermined threshold.

Abstract: In a control device for an internal combustion engine, which includes control unit that has a processor with a plurality of cores and that computes various tasks associated with operation of the internal combustion engine, the control unit includes a selecting unit, that selects at least one core used in the computation from among the plurality of cores, a computing unit that distributes the tasks to the at least one core selected by the selecting unit to perform computation, and an acquisition unit that acquires an engine, rotational speed of the internal combustion engine, and, when the engine rotational speed acquired by the acquisition unit is higher than or equal to a predetermined threshold, the selecting unit increases the number of the cores selected as compared with when the acquired engine rotational speed is lower than the predetermined threshold.

Abstract: A logic verification method for simulating a logic circuit model by using the instruction interpreter, connected to the first and second files, for executing an executable program, includes the steps of: outputting to the second file first status information after the executable program loaded from the first file and already compiled has been executed to an inputted first location; outputting to the second file second status information after the executable program loaded from the first file has been executed to an inputted second location in the instruction interpreter; setting the first status information to the memory unit of the logic circuit model; and outputting to the display, together with the second status information, third status information after the executable program has been executed from the fist location to the second location in the logic circuit model. The first and second locations are assigned by the operator to save the executable program and set an interruption instruction.