Patents by Inventor Keisuke SANUKI

Keisuke SANUKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11984394
    Abstract: A semiconductor memory device including: plural first conductive layers stacked on a substrate; plural second conductive layers each stacked between the first conductive layers; a pillar that extends in a stacking direction of the first and second conductive layers and forms plural memory cells at intersections of the first and second conductive layers in a region where first and second conductive layers are arranged; a first contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the first conductive layers in the region where the first and second conductive layers are arranged; and a second contact plug that extends in the stacking direction of the first and second conductive layers and is connected to the second conductive layers in the region where the first conductive layers and second conductive layers are arranged.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: May 14, 2024
    Assignee: Kioxia Corporation
    Inventors: Keisuke Nakatsuka, Yasuhito Yoshimizu, Tomoya Sanuki, Fumitaka Arai
  • Publication number: 20240086077
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.
    Type: Application
    Filed: March 10, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Tomoya SANUKI, Toshio FUJISAWA, Keisuke NAKATSUKA
  • Patent number: 11923325
    Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Yasuhito Yoshimizu, Takashi Fukushima, Tatsuro Hitomi, Arata Inoue, Masayuki Miura, Shinichi Kanno, Toshio Fujisawa, Keisuke Nakatsuka, Tomoya Sanuki
  • Patent number: 11878504
    Abstract: A plate-making method for manufacturing a printing plate includes: manufacturing the printing plate based on a knockout method in which knockouts of halftone dots in one color are formed, and halftone dots in the other color are overprinted onto positions of the knockouts; for each of pixels, when a sum of a halftone dot area ratio of the one color and a halftone dot area ratio of the other color is smaller than 100%, forming a gap from a knockout in the one color around a halftone dot in the other color; and for each of pixels, when the sum of the halftone dot area ratio of the one color and the halftone dot area ratio of the other color is greater than 100%, forming an overmask such that the halftone dot in the other color penetrates a periphery of the halftone dot in the one color.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: January 23, 2024
    Assignee: TOYO SEIKAN CO., LTD.
    Inventors: Kenichiro Yamamoto, Ryota Nagatsuka, Keisuke Sanuki, Iori Takatori, Yukiko Saito
  • Publication number: 20220212461
    Abstract: A plate-making method for manufacturing a printing plate includes: manufacturing the printing plate based on a knockout method in which knockouts of halftone dots in one color are formed, and halftone dots in the other color are overprinted onto positions of the knockouts; for each of pixels, when a sum of a halftone dot area ratio of the one color and a halftone dot area ratio of the other color is smaller than 100%, forming a gap from a knockout in the one color around a halftone dot in the other color; and for each of pixels, when the sum of the halftone dot area ratio of the one color and the halftone dot area ratio of the other color is greater than 100%, forming an overmask such that the halftone dot in the other color penetrates a periphery of the halftone dot in the one color.
    Type: Application
    Filed: March 24, 2022
    Publication date: July 7, 2022
    Applicant: Toyo Seikan Co., Ltd.
    Inventors: Kenichiro YAMAMOTO, Ryota NAGATSUKA, Keisuke SANUKI, Iori TAKATORI, Yukiko SAITO