Patents by Inventor Keisuke SHIGEMURA

Keisuke SHIGEMURA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11410924
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing steps, memory stack structures extending through the alternating stack, a first contact via structure which contacts a top surface of a respective upper electrically conductive layer in a first step, a first dielectric spacer which does not contact any of the electrically conductive layers other than the respective upper electrically conductive layer in the first step, a second contact via structure which contacts a top surface of a respective lower electrically conductive layer in the first step, and a second dielectric spacer which extends through the respective upper electrically conductive layer, and which contacts the respective lower electrically conductive layer.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: August 9, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Haruki Suwa, Keisuke Shigemura, Akihiro Shimada
  • Publication number: 20220059454
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers containing steps, memory stack structures extending through the alternating stack, a first contact via structure which contacts a top surface of a respective upper electrically conductive layer in a first step, a first dielectric spacer which does not contact any of the electrically conductive layers other than the respective upper electrically conductive layer in the first step, a second contact via structure which contacts a top surface of a respective lower electrically conductive layer in the first step, and a second dielectric spacer which extends through the respective upper electrically conductive layer, and which contacts the respective lower electrically conductive layer.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 24, 2022
    Inventors: Haruki SUWA, Keisuke SHIGEMURA, Akihiro SHIMADA
  • Publication number: 20210358937
    Abstract: A row of backside support pillar structures is formed through a first-tier alternating stack of first-tier insulating layers and first-tier sacrificial material layers. At least one upper-tier alternating stack can be formed, and memory stack structures can be formed through the alternating stacks. A backside trench can be formed through the alternating stacks selective to the row of backside support pillar structures. The sacrificial material layers are replaced with electrically conductive layers, and the backside trench can be filled with a backside trench fill structure, which includes the row of backside support pillar structures. The row of backside support pillar structures reduces or prevents tilting or collapse of the alternating stacks during replacement of the sacrificial material layers with the electrically conductive layers.
    Type: Application
    Filed: December 28, 2020
    Publication date: November 18, 2021
    Inventors: Kohei YAMAGUCHI, Keisuke SHIGEMURA, Kengo KAJIWARA
  • Patent number: 10347647
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: July 9, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Naohiro Hosoda, Keisuke Shigemura, Junichi Ariyoshi, Kazuki Kajitani, Yuji Fukano
  • Publication number: 20190198515
    Abstract: A memory device contains a stack of insulating layers and electrically conductive word line layers, at least one first drain select gate electrode located over the stack and extending through a first drain select transistor and a second drain select transistor, at least one second drain select gate electrode located between the first drain select electrode and the stack, and extending through a third drain select transistor and a fourth drain select transistor. The first drain select transistor and the third drain select transistor are located in a first NAND memory string. The second drain select transistor and the fourth drain select transistor are located in a second NAND memory string different from the first NAND memory string. The first drain select transistor has a higher threshold voltage than the second drain select transistor. The third drain select transistor has a lower threshold voltage than the fourth drain select transistor.
    Type: Application
    Filed: December 21, 2017
    Publication date: June 27, 2019
    Inventors: Naohiro HOSODA, Keisuke SHIGEMURA, Junichi ARIYOSHI, Kazuki KAJITANI, Yuji FUKANO
  • Patent number: 10083982
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: September 25, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Keisuke Shigemura, Junichi Ariyoshi, Masanori Tsutsumi, Michiaki Sano, Yanli Zhang, Raghuveer S. Makala
  • Publication number: 20180138194
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack having a memory array region and a contact region containing stepped surfaces, and memory stack structures having a semiconductor channel and a memory film extending through the memory array region of the alternating stack. The electrically conductive layers include a drain select gate electrode and word lines, where the drain select gate electrode is thicker than each of the word lines.
    Type: Application
    Filed: April 25, 2017
    Publication date: May 17, 2018
    Inventors: Keisuke SHIGEMURA, Junichi ARIYOSHI, Masanori TSUTSUMI, Michiaki SANO, Yanli ZHANG, Raghuveer S. MAKALA