Abstract: An address decoder has a plurality of address comparator circuits for respective address areas, each comparator circuit including a base address register, a mask register, an AND gate, and a comparator. An address data outputted from a processor is inputted to the address comparator where the AND circuit takes an AND logic of each bit for the address and an inverted value taken for each bit from the content of the mask register and the result is compared to a starting address of the pertinent address area stored in the base address register. If the compared data are in accord, an address decoded signal of "1" is outputted, which indicates that the address is an address within the pertinent address area. The address comparators and function in the same way as the address comparator.

Abstract: A microprocessor with a bus sizing function has internal data bus and external data bus having 2.sup.n bit width, in which n is a natural number, for inputting and outputting data to and from said data path, 2.sup.n interface circuits having a bus sizing function for using as a bus of 2.sup.m bits, in which m is a natural number smaller than n, said interface circuit being connected to 2.sup.n-m of internal data buses and 2.sup.n pads for connecting said internal data bus to the external data bus via said interface circuit. Among said interface circuit and said pads, 2.sup.n-m of said interface circuits and said pads associated with common internal data bus are aggregated as a block and arranged at close proximity to each other.