Patents by Inventor Keisuke SUDA

Keisuke SUDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230307050
    Abstract: A semiconductor memory device includes memory blocks arranged in a first direction and bit lines that are arranged in a second direction, and are arranged with the memory blocks in a third direction. The memory block includes first conductive layers arranged in the third direction, a second conductive layer disposed on a side opposite to the bit lines in the third direction with respect to the first conductive layers, semiconductor layers that extend in the third direction, are opposed to the first conductive layers, have one ends in the third direction electrically connected to the second conductive layer, and have the other ends in the third direction electrically connected to the bit lines, and electric charge accumulating films disposed between the first conductive layers and the semiconductor layers. The first conductive layers and the second conductive layer are separated between the memory blocks.
    Type: Application
    Filed: September 13, 2022
    Publication date: September 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Keisuke SUDA, Ryota SUZUKI, Kenta YAMADA
  • Publication number: 20230276626
    Abstract: A semiconductor storage device includes: a first semiconductor layer through first conductive layers; a gate insulating film between the first conductive layers and the first semiconductor layer; a first structure facing the first conductive layers; a second semiconductor layer connected to the first semiconductor layer and the first structure; a third semiconductor layer between the second semiconductor layer and the first conductive layers; a fourth semiconductor layer including a first portion along a bottom surface of the third semiconductor layer and a second portion along a top surface of the second semiconductor layer; and a first insulating layer, between the first and second portions, including a first region spaced from the first structure with a distance longer than a first distance that contains a nitride film, and a second region spaced from the first structure with a distance shorter than the first distance that does not contain nitrogen.
    Type: Application
    Filed: August 30, 2022
    Publication date: August 31, 2023
    Applicant: Kioxia Corporation
    Inventors: Hideto TAKEKIDA, Keisuke SUDA, Naoyuki IIDA, Kohei NYUI, Ryo HIKIDA
  • Publication number: 20230262983
    Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor layer arranged above a substrate in a first direction; a first interconnect layer between the substrate and the semiconductor layer; a second interconnect layer arranged adjacent to the first interconnect layer in a second direction; a plurality of memory pillars; and a first member between the first interconnect layer and the second interconnect layer. The semiconductor layer has, on a side of a second surface facing a first surface in contact with the first member, a first projecting portion projecting in the first direction and overlapping a part of an area in the first direction, the area being provided with the first interconnect layer and the first member.
    Type: Application
    Filed: September 13, 2022
    Publication date: August 17, 2023
    Applicant: Kioxia Corporation
    Inventors: Hisashi HARADA, Keisuke SUDA
  • Patent number: 11637123
    Abstract: A semiconductor device according to one embodiment is provided with: a substrate; a stacked body provided on the substrate; and a pillar portion penetrating the stacked body. The pillar portion has a first film including a first material and a second material, and a second film provided on an inner side of the first film. The second material is a material that increases an etching rate of the first material as a composition rate relative to the first material is higher, and the composition rate gradually decreases from an upper part to a lower part of the first film.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: April 25, 2023
    Assignee: Kioxia Corporation
    Inventors: Atsushi Fukumoto, Keisuke Suda, Takayuki Ito
  • Publication number: 20230086773
    Abstract: According to one embodiment, a semiconductor memory device includes: a stacked body having a stacked structure in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, the stacked body including a memory region and a dummy region arranged in a first direction intersecting a stacking direction of the plurality of conductive layers, the dummy region including a first stepped portion in which at least a part of the plurality of conductive layers on an upper layer side is processed in a stepped shape and terminates at an end portion opposite to the memory region in the first direction; and first and second plate-like portions extending in the stacking direction and the first direction in the stacked body at positions in the memory region away from each other in a second direction intersecting the stacking direction and the first direction, the first and second plate-like portions being directly or indirectly connected to each other and terminating in the d
    Type: Application
    Filed: March 14, 2022
    Publication date: March 23, 2023
    Applicant: Kioxia Corporation
    Inventors: Akira YOTSUMOTO, Keisuke SUDA, Kenji TASHIRO, Tetsuya YAMASHITA, Daigo ICHINOSE
  • Publication number: 20220115403
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki MARUYAMA, Yoshiaki FUKUZUMI, Yuki SUGIURA, Shinya ARAI, Fumie KIKUSHIMA, Keisuke SUDA, Takashi ISHIDA
  • Publication number: 20220077170
    Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.
    Type: Application
    Filed: November 12, 2021
    Publication date: March 10, 2022
    Inventors: Yoshiaki FUKUZUMI, Keisuke SUDA, Fumiki AISO, Atsushi FUKUMOTO
  • Publication number: 20210082952
    Abstract: A semiconductor device according to one embodiment is provided with: a substrate; a stacked body provided on the substrate; and a pillar portion penetrating the stacked body. The pillar portion has a first film including a first material and a second material, and a second film provided on an inner side of the first film. The second material is a material that increases an etching rate of the first material as a composition rate relative to the first material is higher, and the composition rate gradually decreases from an upper part to a lower part of the first film.
    Type: Application
    Filed: August 10, 2020
    Publication date: March 18, 2021
    Applicant: Kioxia Corporation
    Inventors: Atsushi Fukumoto, Keisuke Suda, Takayuki Ito
  • Publication number: 20200391534
    Abstract: A pseudo etching decoration method and a pseudo etching decoration product in which decoration that appears as if a decoration target is etched can be provided to the decoration target without actually performing etching are provided. The pseudo etching decoration method includes: a process (S51) of providing a matte-tone coating to the decoration target; and a process (S52) of forming a gloss-tone film of clear ink on part of the surface of the decoration target by providing gloss-tone printing with the clear ink by UV ink-jet printing on part of the matte-tone coating provided to the decoration target in the process at S51.
    Type: Application
    Filed: June 11, 2020
    Publication date: December 17, 2020
    Applicant: MIMAKI ENGINEERING CO., LTD.
    Inventor: Keisuke Suda
  • Patent number: 10510770
    Abstract: A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: December 17, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hisashi Harada, Jun Nishimura, Ayaha Hachisuga, Hiroshi Nakaki, Yukie Miyazaki, Keisuke Suda, Yu Hirotsu
  • Publication number: 20190355742
    Abstract: A semiconductor memory device includes a plurality of electrode layers stacked above a first semiconductor layer, a second semiconductor layer and a first film. The second semiconductor layer extends through the plurality of electrode layers in a stacking direction of the plurality of electrode layers. The second semiconductor layer includes an end portion inside the first semiconductor layer. The first film is positioned inside the first semiconductor layer and contacts the first semiconductor layer. The first semiconductor layer includes a first portion, a second portion, and a third portion. The first film is positioned between the first portion and the second portion. The third portion links the first portion and the second portion. The third portion is positioned between the first film and the second semiconductor layer. The second semiconductor layer includes a contact portion contacting the third portion of the first semiconductor layer.
    Type: Application
    Filed: March 8, 2019
    Publication date: November 21, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki MARUYAMA, Yoshiaki Fukuzumi, Yuki Sugiura, Shinya Arai, Fumie Kikushima, Keisuke Suda, Takashi Ishida
  • Publication number: 20190326310
    Abstract: A semiconductor memory includes a substrate, a source line layer above the substrate in a memory region and a peripheral region of the substrate, a first insulating layer above the source line layer, a first conductive layer on the first insulating layer in the memory and peripheral regions, an alternating stack of a plurality of second insulating layers and a plurality of second conductive layers on the first conductive layer in the memory region, and a plurality of pillars extending through the alternating stack of the second insulating layers and the second conductive layers, the first conductive layer, and the first insulating layer in the memory region. A bottom end of each of the pillars is in the source line layer in a thickness direction. A carrier density of the source line layer is higher in the memory region than in the peripheral region.
    Type: Application
    Filed: March 4, 2019
    Publication date: October 24, 2019
    Inventors: Yoshiaki FUKUZUMI, Keisuke SUDA, Fumiki AISO, Atsushi FUKUMOTO
  • Publication number: 20190287998
    Abstract: A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.
    Type: Application
    Filed: September 11, 2018
    Publication date: September 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Hisashi HARADA, Jun NISHIMURA, Ayaha HACHISUGA, Hiroshi NAKAKI, Yukie MIYAZAKI, Keisuke SUDA, Yu HIROTSU
  • Patent number: 9831187
    Abstract: Provided is a resist film forming device which uses an electrostatic spray device which is capable of forming a thin film with a uniform thickness on a workpiece. A resist film forming device (100), which forms a resist film (108) on a substrate by electrostatic spraying, comprises: a nozzle (102) which, upon application of a prescribed voltage, sprays liquid particles which form the raw material for a resist film (108) toward a substrate (105) having stepped portions (105a); a driving means (111) for causing relative movement of the substrate (105) or the nozzle (102); and a control means (110) for controlling such that the resist film (108) is formed on the substrate (105) having the stepped portions (105a) by the liquid particles.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: November 28, 2017
    Assignee: Apic Yamada Corporation
    Inventors: Kazuhiko Kobayashi, Keisuke Suda
  • Patent number: 9685664
    Abstract: A fuel cell stack includes fuel cells, a reactant gas channel, a reactant gas inlet manifold, a reactant gas outlet manifold, an inlet buffer portion, and an outlet buffer portion. A reactant gas flows through the reactant gas channel along a surface of a separator. The reactant gas flows through the reactant gas inlet manifold and the reactant gas outlet manifold in a stacking direction. The inlet buffer portion connects an inlet of the reactant gas channel to the reactant gas inlet manifold. The inlet buffer portion includes linear inlet guide protrusions. Inlet guide channels are provided between the linear inlet guide protrusions and connect the reactant gas inlet manifold to the reactant gas channel. A pitch between the linear inlet guide protrusions increases in accordance with an increase in a distance from the reactant gas inlet manifold to the linear inlet guide protrusions.
    Type: Grant
    Filed: January 8, 2015
    Date of Patent: June 20, 2017
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Kenji Nagumo, Kentaro Ishida, Keisuke Suda, Yuji Asano, Akihiro Matsui
  • Publication number: 20170077042
    Abstract: Provided is a resist film forming device which uses an electrostatic spray device which is capable of forming a thin film with a uniform thickness on a workpiece. A resist film forming device (100), which forms a resist film (108) on a substrate by electrostatic spraying, comprises: a nozzle (102) which, upon application of a prescribed voltage, sprays liquid particles which form the raw material for a resist film (108) toward a substrate (105) having stepped portions (105a); a driving means (111) for causing relative movement of the substrate (105) or the nozzle (102); and a control means (110) for controlling such that the resist film (108) is formed on the substrate (105) having the stepped portions (105a) by the liquid particles.
    Type: Application
    Filed: November 28, 2016
    Publication date: March 16, 2017
    Applicant: Apic Yamada Corporation
    Inventors: Kazuhiko KOBAYASHI, Keisuke SUDA
  • Patent number: 9589907
    Abstract: Provided is a resist film forming device which uses an electrostatic spray device which is capable of forming a thin film with a uniform thickness on a workpiece. A resist film forming device (100), which forms a resist film (108) on a substrate by electrostatic spraying, comprises: a nozzle (102) which, upon application of a prescribed voltage, sprays liquid particles which form the raw material for a resist film (108) toward a substrate (105) having stepped portions (105a); a driving means (111) for causing relative movement of the substrate (105) or the nozzle (102); and a control means (110) for controlling such that the resist film (108) is formed on the substrate (105) having the stepped portions (105a) by the liquid particles.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: March 7, 2017
    Assignee: Apic Yamada Corporation
    Inventors: Kazuhiko Kobayashi, Keisuke Suda
  • Patent number: 9293779
    Abstract: A fuel cell includes a membrane electrode assembly, a first separator, and a second separator. The second separator has a fuel gas flow field connected to a fuel gas supply passage and a fuel gas discharge passage. The fuel gas flow field includes a plurality of corrugated flow grooves and a flat flow field. The corrugated flow grooves extend in the horizontal direction, respectively, and are arranged in the direction of the gravity. The flat flow field is provided within a power generation area, at the lowermost position in the direction of the gravity, and extends in the horizontal direction.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: March 22, 2016
    Assignee: Honda Motor Co., Ltd.
    Inventors: Seiji Sugiura, Shuhei Goto, Kenichi Murakami, Kentaro Ishida, Keisuke Suda
  • Publication number: 20150303151
    Abstract: Provided is a resist film forming device which uses an electrostatic spray device which is capable of forming a thin film with a uniform thickness on a workpiece. A resist film forming device (100), which forms a resist film (108) on a substrate by electrostatic spraying, comprises: a nozzle (102) which, upon application of a prescribed voltage, sprays liquid particles which form the raw material for a resist film (108) toward a substrate (105) having stepped portions (105a); a driving means (111) for causing relative movement of the substrate (105) or the nozzle (102); and a control means (110) for controlling such that the resist film (108) is formed on the substrate (105) having the stepped portions (105a) by the liquid particles.
    Type: Application
    Filed: November 11, 2013
    Publication date: October 22, 2015
    Applicant: Apic Yamada Corporation
    Inventors: Kazuhiko KOBAYASHI, Keisuke SUDA
  • Publication number: 20150200414
    Abstract: A fuel cell stack includes fuel cells, a reactant gas channel, a reactant gas inlet manifold, a reactant gas outlet manifold, an inlet buffer portion, and an outlet buffer portion. A reactant gas flows through the reactant gas channel along a surface of a separator. The reactant gas flows through the reactant gas inlet manifold and the reactant gas outlet manifold in a stacking direction. The inlet buffer portion connects an inlet of the reactant gas channel to the reactant gas inlet manifold. The inlet buffer portion includes linear inlet guide protrusions. Inlet guide channels are provided between the linear inlet guide protrusions and connect the reactant gas inlet manifold to the reactant gas channel. A pitch between the linear inlet guide protrusions increases in accordance with an increase in a distance from the reactant gas inlet manifold to the linear inlet guide protrusions.
    Type: Application
    Filed: January 8, 2015
    Publication date: July 16, 2015
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Kenji NAGUMO, Kentaro ISHIDA, Keisuke SUDA, Yuji ASANO, Akihiro MATSUI