Abstract: A data bus structure, a driver therewith, and a display with a driver capable of low power consumption are provided herewith. In the proposed structure, data lines of the data bus corresponding to a plurality of output channels are divided by alternatively inserting isolating elements. By controlling these isolating elements, current will be alternatively isolated from a portion of the bus and power consumption is significantly reduced. In the proposed structure, different function and settings can be determined in advance in consideration of where data is taken into the bus line.

Abstract: This invention provides a type of sense amplifier, a type of bit line circuit, a type of storage device, and a method for amplifying a read signal characterized by the fact that it has a small detection error of the read signal and has low power consumption. With bit lines (BL, BLZ) and input terminals (SA, SAZ) of the amplifier connected to each other by means of a CMOS switch circuit, as control signal ENN becomes high level, amplification of the read signal in the amplifier starts and, at the same time, the amplified signal is held. After a time delay determined by delay circuit U1 from the start of amplification of the read signal, control signal GEN1 and control signal GEN2 output from said delay circuit U1 are changed, and connection between the bit line and amplifier is cut off.

Abstract: This invention provides a type of sense amplifier, a type of bit line circuit, a type of storage device, and a method for amplifying a read signal characterized by the fact that it has a small detection error of the read signal and has low power consumption. With bit lines (BL, BLZ) and input terminals (SA, SAZ) of the amplifier connected to each other by means of a CMOS switch circuit, as control signal ENN becomes high level, amplification of the read signal in the amplifier starts and, at the same time, the amplified signal is held. After a time delay determined by delay circuit U1 from the start of amplification of the read signal, control signal GEN1 and control signal GEN2 output from said delay circuit U1 are changed, and connection between the bit line and amplifier is cut off.