Abstract: A throttle operating device includes a fixing member, a throttle lever, and a detection sensor. A drive source of the transport is configured to be controlled based on the rotational operation angle of the throttle lever detected by the detection sensor. The throttle lever is configured to be rotated in a forward direction and a reverse direction. When the throttle lever is rotated in the forward direction, the drive source of the transport can be controlled. When the throttle lever is rotated in the reverse direction, a predetermined device mounted on the transport can be operated or an operation of the predetermined device can be stopped.

Abstract: A throttle operating device includes a fixing member, a throttle lever, and a detection sensor. A drive source of the transport is configured to be controlled based on the rotational operation angle of the throttle lever detected by the detection sensor. The throttle lever is configured to be rotated in a forward direction and a reverse direction. When the throttle lever is rotated in the forward direction, the drive source of the transport can be controlled. When the throttle lever is rotated in the reverse direction, a predetermined device mounted on the transport can be operated or an operation of the predetermined device can be stopped.

Abstract: First memory openings are formed through a first alternating stack of first insulating layers and first spacer material layers. Each first memory opening is filled with a first memory film, a sacrificial dielectric liner, and a first-tier opening fill material portion. Second memory openings are formed through a second alternating stack of second insulating layers and second spacer material layers. A second memory film is formed in each second memory opening. The first-tier opening fill material portions are removed selective to the sacrificial dielectric liners. The sacrificial dielectric liners are removed selective to the second memory films and the first memory films. A vertical semiconductor channel can be formed on each vertical stack of a first memory film and a second memory film.

Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Abstract: In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).

Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET, Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Abstract: In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).

Abstract: In an integrated-circuit memory, performance is increased by reducing an electrical contact resistance between a metal layer and an upper poly layer (a control gate poly). The electrical contact resistance is reduced by increasing the thickness of a silicide layer between the metal layer and the upper poly layer. The memory has a memory cell region and a non-memory cell region. The thickness of the silicide layer is typically restricted by consideration of integrated-circuit fabrication geometry for each memory cell not to exceed a predetermined aspect ratio. The present implementation allows independent optimization of the thickness of silicide layer in the memory cells region and the non-memory cell region. In particular, in the non-memory cell region, a thicker silicide layer significantly improves the contact resistance of a slit contact for components having the upper poly layer in contact with a lower poly layer (a floating gate poly).

Abstract: This information terminal (1) includes a terminal display portion (12) and a control portion (11) performing control of transmitting an image signal configured to display an image on an external display device (2). The control portion is configured to perform control of acquiring information about the posture of the external display device and transmitting the image signal of the image according to the posture of the external display device to the external display device on the basis of the information about the posture which has been acquired.

Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Abstract: An image output apparatus includes an image processing component, an OSD production component and an output component. The image processing component is configured to perform an image processing on input image data to generate processed image data. The OSD production component is configured to produce OSD data that specifies color data according to a display characteristic of a display apparatus that is configured to be connected to the image output apparatus. The output component is configured to combine the OSD data with the processed image data to output output image data.

Abstract: In a television, which can be connected to a portable information terminal, it is possible to display video based on the data of a multimedia file stored on a storage medium even in cases where there is no built-in decoder. In cases where a TV itself does not possess a decoder which can decode the data of a multimedia file selected by the user from the multimedia files stored on the USB memory, the CPU of the TV transmits to a smartphone the data of the selected multimedia file and a decoding request command to request that the data be decoded, thus receiving a video signal and/or an audio signal obtained by various types of decoders of the smartphone. Consequently, the CPU of the TV can output video and/or audio to a display unit and a speaker on the basis of the data of the selected multimedia file.

Abstract: A performance and reliability of a semiconductor device are improved. On a semiconductor substrate, a gate electrode for a first MISFET and a dummy gate electrode for a second MISFET are formed, and then, an insulating film is partially formed on the gate electrode. Then, on the semiconductor substrate, an insulating film is formed so as to cover the dummy gate electrode, the gate electrode and other insulating film. Then, the dummy gate electrode is exposed by polishing the insulating film. In this polishing, the insulating film is polished under a condition that a polishing speed of the other insulating film is smaller than a polishing speed of the insulating film. Then, after the dummy gate electrode is removed, the gate electrode for the second MISFET is formed in a region where the dummy gate electrode has been removed.

Abstract: A control gate electrode and a memory gate electrode of a memory cell of a non-volatile memory are formed in a memory cell region of a semiconductor substrate, and a dummy gate electrode is formed in a peripheral circuit region. Then, n+-type semiconductor regions for a source or a drain of the memory cell are formed in the memory cell region and n+-type semiconductor regions for a source or a drain of MISFET are formed in the peripheral circuit region. Then, a metal silicide layer is formed over the n+-type semiconductor regions but the metal silicide layer is not formed over the control gate electrode, the memory gate electrode, and the gate electrode. Subsequently, the gate electrode is removed and replaced with the gate electrode for MISFET. Then, after removing the gate electrode and replacing it with a gate electrode for MISFET, a metal silicide layer is formed over the memory gate electrode and the control gate electrode.

Abstract: The semiconductor device includes a memory cell including a plurality of magnetoresistive elements disposed therein, and a peripheral circuit region disposed around the memory cell region. The magnetoresistive element includes a magnetization fixed layer, a magnetization free layer, and a tunneling insulation layer. The semiconductor device includes, above the magnetoresistive elements, a plurality of first wires extending in the direction along the main surface. In the peripheral circuit region, there is disposed a multilayer structure of lamination of a layer equal in material to the magnetization free layer, a layer equal in material to the tunneling insulation layer, and a layer equal in material to the magnetization fixed layer so as to overlap a second wire formed of the same layer as the first wire in plan view. The multilayer structure does not overlap both of a pair of adjacent second wires in plan view in the peripheral circuit region.

Abstract: A digital broadcast recording device includes a receiving component, a program information memory component, a first setting component, a second setting component, an extraction component and a recording execution component. The first setting component sets a recording condition based on a first operation input. The recording condition indicates whether to record program information corresponding to one physical channel, or to record program information corresponding to a subset of a specific number of sub-channels included in the one physical channel. The second setting component sets a channel number corresponding to the subset of the specific number of the sub-channels based on a second operation input. The extraction component extracts the program information corresponding to the subset of the specific number of the sub-channels set by the second setting component. The recording execution component records the program information to the program information memory component.

Abstract: To provide a semiconductor device that has an improved adhesion between a bottom conductive layer and a protection film protecting an MTJ element. This semiconductor device includes a bottom electrode formed over a semiconductor substrate, an MTJ element part formed over a part of the bottom electrode by lamination of a bottom magnetic film, an insulating film, a top magnetic film, and a top electrode in this order, and a protection film formed over the bottom electrode so as to cover the MTJ element part, wherein the bottom electrode is formed by amorphized metal nitride and the protection film is formed by an insulating film containing nitrogen.

Abstract: There are provided a semiconductor device in which short circuit failures in magnetic resistor elements and the like are reduced, and a method of manufacturing the same. An interlayer insulating film in which memory cells are formed is formed such that the upper surface of the portion of the interlayer insulating film located in a memory cell region where the magnetic resistor elements are formed is at a position lower than that of the upper surface of the portion of the interlayer insulating film located in a peripheral region. Another interlayer insulating film is formed so as to cover the magnetic resistor elements. In the another interlayer insulating film, formed are bit lines electrically coupled to the magnetic resistor elements. Immediately below the magnetic resistor elements, formed are digit lines.