Patents by Inventor Keisuke UNOSAWA

Keisuke UNOSAWA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9166108
    Abstract: A semiconductor light-emitting device has a first principal surface, a second principal surface formed on a side opposite to the first principal surface, and a light-emitting layer. A p-electrode on the second principal surface is in the region of the light-emitting layer and surrounds an n-electrode. An insulating layer on the side of the semiconductor layer surrounds the p-and the n-electrodes. A p-metal pillar creates an electrical connection for the p-electrode, and an n-metal pillar creates an electrical connection for the n-electrode. A resin layer surrounds the end portions of the p-and the n-metal pillars, and also covers the side surface of the semiconductor layer, the second principal surface, the p-electrode, the n-electrode, the insulating layer, the p-metal pillar and the n-metal pillar.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Unosawa
  • Publication number: 20140299909
    Abstract: A semiconductor light-emitting device has a first principal surface, a second principal surface formed on a side opposite to the first principal surface, and a light-emitting layer. A p-electrode on the second principal surface is in the region of the light-emitting layer and surrounds an n-electrode. An insulating layer on the side of the semiconductor layer surrounds the p-and the n-electrodes. A p-metal pillar creates an electrical connection for the p-electrode, and an n-metal pillar creates an electrical connection for the n-electrode. A resin layer surrounds the end portions of the p-and the n-metal pillars, and also covers the side surface of the semiconductor layer, the second principal surface, the p-electrode, the n-electrode, the insulating layer, the p-metal pillar and the n-metal pillar.
    Type: Application
    Filed: May 27, 2014
    Publication date: October 9, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Keisuke UNOSAWA
  • Patent number: 8766294
    Abstract: A semiconductor light-emitting device has a first principal surface, a second principal surface formed on a side opposite to the first principal surface, and a light-emitting layer. A p-electrode on the second principal surface is in the region of the light-emitting layer and surrounds an n-electrode. An insulating layer on the side of the semiconductor layer surrounds the p- and the n-electrodes. A p-metal pillar creates an electrical connection for the p-electrode, and an n-metal pillar creates an electrical connection for the n-electrode. A resin layer surrounds the end portions of the p- and the n-metal pillars, and also covers the side surface of the semiconductor layer, the second principal surface, the p-electrode, the n-electrode, the insulating layer, the p-metal pillar and the n-metal pillar.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keisuke Unosawa
  • Publication number: 20130146933
    Abstract: A semiconductor light-emitting device has a first principal surface, a second principal surface formed on a side opposite to the first principal surface, and a light-emitting layer. A p-electrode on the second principal surface is in the region of the light-emitting layer and surrounds an n-electrode. An insulating layer on the side of the semiconductor layer surrounds the p- and the n-electrodes. A p-metal pillar creates an electrical connection for the p-electrode, and an n-metal pillar creates an electrical connection for the n-electrode. A resin layer surrounds the end. portions of the p- and the n-metal pillars, and also covers the side surface of the semiconductor layer, the second principal surface, the p-electrode, the n-electrode, the insulating layer, the p-metal pillar and the n-metal pillar.
    Type: Application
    Filed: December 6, 2012
    Publication date: June 13, 2013
    Inventor: Keisuke UNOSAWA
  • Publication number: 20080293251
    Abstract: A method for manufacturing a semiconductor device in which a first hole and a second hole having a lower aspect ratio than the first hole are formed in an insulating film formed on a semiconductor substrate is provided. The method includes: performing a first etching process configured to etch the insulating film; and performing a second etching process configured to etch the insulating film. The second etching process is performed under a condition that deposition rate of a deposited layer formed on a surface of the insulating film is lower than that in the first etching process.
    Type: Application
    Filed: March 21, 2008
    Publication date: November 27, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuaki AOKI, Hiroshi KATSUMATA, Keisuke UNOSAWA