Patents by Inventor Keisuke Yasui

Keisuke Yasui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210089234
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory device to store data; and a memory controller configured to: manage first information allocated to each user and including first management data; perform first processing for an access to the nonvolatile memory device when an access request to the nonvolatile memory device has been received from the user and the first management data is equal to or larger than a first value; and perform second processing for an access to the nonvolatile memory device when the first management data is equal to or larger than a second value.
    Type: Application
    Filed: March 13, 2020
    Publication date: March 25, 2021
    Applicants: Kioxia Corporation, TOSHIBA INFORMATION SYSTEMS (JAPAN) CORPORATION
    Inventors: Keisuke YASUI, Ryuji NISHIKUBO, Norio AOYAMA
  • Publication number: 20160014698
    Abstract: According to one embodiment, a method for controlling an electronic apparatus capable of communicating with a wearable electronic device includes: restricting at least one function of the electronic apparatus based on a signal received from the wearable electronic device, the signal being usable in measuring a distance between the wearable electronic device and the electronic apparatus; and reducing traffic of the signal between the wearable electronic device and the electronic apparatus from a first level to a second level while the electronic apparatus is directly operated by a user.
    Type: Application
    Filed: January 26, 2015
    Publication date: January 14, 2016
    Inventors: Keisuke YASUI, Kouichi OGI
  • Patent number: 7950998
    Abstract: A collective system for billing management of each game machine installed in shops or the like via communication network. A limit is set to the usable number, while the game machine is ensured continuous use as long as it is properly used and the billing is carried out regularly during the continuous use on a pay-per-use basis. The play count is counted up every time one game is played, and when the play count has reached or exceeded a count limit, the use of the game machine is restricted. The game machine is connected to a billing server via a communication network. The billing server includes a count limit renewing unit which renews the count limit of the game machine that has transmitted billing information, and transmits the new count limit back to the game machine every time the billing server receives the billing information from the game machine.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: May 31, 2011
    Assignee: Sega Corporation
    Inventors: Noriaki Ueda, Keisuke Yasui, Yoichi Tanaami, Shinich Furuhashi, Yusuke Shimizu, Kazunori Nishisaka, Yuki Yamanaka, Mio Kanie
  • Publication number: 20100333103
    Abstract: According to one embodiment, an information processor includes a management module that manages a plurality of register areas in a host controller for processing data protected by copyright. The register areas store confidential information for copyright protection. The management module includes a use state management module and a release module. The use state management module manages use state information on whether the register areas are used by existing process tasks. When all the register areas are occupied by the existing process tasks and a new process task requests for the use of a register area to perform a process based on the confidential information, the release module releases a register area occupied by one of the existing process tasks according to the use state information to assign the register area to the new process task.
    Type: Application
    Filed: June 7, 2010
    Publication date: December 30, 2010
    Inventors: Naomiki Kobayashi, Hiroki Iwahara, Jun Sato, Keisuke Yasui, Fumio Yoshiya, Keiko Watanabe, Jun Ohashi
  • Publication number: 20090089488
    Abstract: According to one embodiment, there is disclosed a memory system comprising a flash memory unit which suspends a write operation to execute a read operation when receiving a suspend command during a write operation, a CPU, an OS which includes a device driver, a TLB which has a page table for conversion from a virtual address to a physical address, and an application program which makes a TLB setting request with respect to the device driver when receiving a read command under the control of the CPU and the OS, acquires address information read from the page table of the TLB by the device driver in response to the setting request, and executes read directly with respect to the flash memory unit using the acquired address information without using the device driver.
    Type: Application
    Filed: September 22, 2008
    Publication date: April 2, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Keisuke Yasui
  • Publication number: 20080000750
    Abstract: A collective system for billing management of each game machine installed in shops or the like via communication network. A limit is set to the usable number, while the game machine is ensured continuous use as long as it is properly used and the billing is carried out regularly during the continuous use on a pay-per-use basis. The play count is counted up every time one game is played, and when the play count has reached or exceeded a count limit, the use of the game machine is restricted. The game machine is connected to a billing server via a communication network. The billing server includes a count limit renewing unit which renews the count limit of the game machine that has transmitted billing information, and transmits the new count limit back to the game machine every time the billing server receives the billing information from the game machine.
    Type: Application
    Filed: May 30, 2007
    Publication date: January 3, 2008
    Inventors: Noriaki Ueda, Keisuke Yasui, Yoichi Tanaami, Shinich Furuhashi, Yusuke Shimizu, Kazunori Nishisaka, Yuki Yamanaka, Mio Kanie
  • Publication number: 20040127288
    Abstract: A communication game equipment is provided, which is capable of implementing a system for performing real time communication multiplayer communication and real time management monitoring communication while concurrently keeping an equipment load level. The communication game equipment including a main system having a main CPU, which controls execution of games by game programs; and a communication sub-system having a sub-CPU, which executes a plurality of different communication function tasks, wherein the communication sub-system is provided with a shared memory accessible by the main CPU and the sub-CPU, the communication sub-system having a resource management task function, which manages resources of the shared memory for the plurality of different communication function tasks.
    Type: Application
    Filed: July 23, 2003
    Publication date: July 1, 2004
    Inventors: Shinichi Furuhashi, Keisuke Yasui, Jiro Yoshida, Youichi Tanaami
  • Patent number: 6680741
    Abstract: A computer graphic system wherein image element data can be processed efficiently at a high speed, and images of higher quality are produced at a lower cost than conventional. An image processor for dividing a screen into regions (fragments) of predetermined sizes and processing data on every divided region (fragment), wherein pieces of information on image constituting elements are rearranged in a direction vertical to a scanning line (ST1), the pieces of information on the image constituting elements are rearranged in a direction parallel to the scanning line (ST2), and image processing for opaque polygons, polygons with transparent pixels, and semitransparent polygons is performed in the order of mention on the basis of the rearranged pieces of information (ST3 to ST6).
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: January 20, 2004
    Assignee: Sega Enterprises, Ltd.
    Inventors: Keisuke Yasui, Seisuke Morioka, Jun Okubo
  • Patent number: 6356264
    Abstract: According to the image processing method, when the number of shadow polygons existing between a depth position of pixels of ordinary polygons subject to shadowing and an infinite position is counted and that number is an odd number, those pixels are unconditionally judged to be positioned inside a region of shadow volume. Therefore, regions to undergo shadowing can be efficiently detected by judging whether the number is an odd number or an even number at all pixel positions.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: March 12, 2002
    Assignee: Sega Enterprises, Ltd.
    Inventors: Keisuke Yasui, Jun Okubo
  • Patent number: 6333742
    Abstract: A table is used in forming spotlight characteristics that impart illumination effects to polygon images displayed by an image processing system, and the number of light sources that can be used in an image scene is increased above the number of light sources that can be used simultaneously. In order to realize this, a method of forming spotlight effect characteristics attached to pixels configuring polygons is proposed wherein a plurality of characteristic values corresponding to a prescribed spotlight characteristic curve is held in a table, and said spotlight characteristic curve is formed from characteristic values read out from the table and from interpolated values found by interpolating between adjacent characteristic values. Inner products are found between spot light axis vectors and light vectors extending toward pixels, these values of inner products so found are used as addresses, and characteristic values are read out from appropriate addresses of the table.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: December 25, 2001
    Assignee: Sega Enterprises, Ltd.
    Inventors: Seisuke Morioka, Keisuke Yasui
  • Patent number: 6320580
    Abstract: Disclosed are an image processing apparatus and an image processing method, which can efficiently execute a hidden-surface process, a blending process on translucent polygons and a shading process by a light source all in a rendering process.
    Type: Grant
    Filed: November 2, 1998
    Date of Patent: November 20, 2001
    Assignee: Sega Enterprises, Ltd.
    Inventors: Keisuke Yasui, Jun Okubo, Seisuke Morioka, Junichi Naoi
  • Patent number: 6271848
    Abstract: The present invention conducts rendering processing according to a prescribed priority relating to each polygon attribute. For example, rendering for semi-transparent polygons is conducted after rendering for opaque polygons. By this means, it is possible to carry out rendering for semi-transparent polygons reliably. Furthermore, rendering for polygons containing transparent portions is conducted after rendering for polygons not containing transparent portions. By this means, it is possible to reduce rendering processing for polygons containing transparent portions, as far as possible. Moreover, rendering processing is carried out for all background polygons together. Thereby, it is possible to carry out suitable depth cue processing for polygons positioned in the far distance of the screen.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: August 7, 2001
    Assignee: Sega Enterprises, Ltd.
    Inventors: Keisuke Yasui, Kazuyoshi Kasai
  • Patent number: 6249272
    Abstract: An image processing method and device corrects an empty dot between Polygons on a video screen at high speed without unnecessarily deforming a shape of the Polygons. Three latches 10, 12, 14 are provided, and a pattern detecting and correcting circuit 30 is inserted between the latches 12, 14. Data of a dot is inputted from the latch 10 and shifted to the right in synchronization with clocks. The pattern detecting and correcting circuit 30 checks a pattern of presence of image data of the continuous four dots along a scan line, based on fill data of the dot data D1, D2, D3, D4, and corrects the inputted dot data D3 to dot data D3′ as required to output the corrected dot data D3′ to the latch 14.
    Type: Grant
    Filed: August 23, 1996
    Date of Patent: June 19, 2001
    Assignee: Sega Enterprises, Ltd.
    Inventors: Hiroshi Yagi, Keisuke Yasui
  • Patent number: 6239809
    Abstract: The present invention relates to an image processing device comprising a rendering processing section for generating color data for pixels which are to be displayed from polygon data including at least a polygon ID, positional co-ordinates data and parameters for generating color data attributed thereto. The image processing device includes a polygon buffer memory for storing color data for pixels in a flame. The rendering processing section includes a first processing section (242, 243, 244, 245) for generating Z values of pixels in respective polygons in the frame and for storing Z values for pixels to be displayed on the screen and the polygon ID corresponding thereto in a Z value buffer memory. The rendering processing section includes a second processing section (246, 247, 248) for generating color data from the parameters attributed to the polygon IDs stored in the Z buffer memory for each pixels in the frame and for storing the color data in the frame buffer memory.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: May 29, 2001
    Assignee: Sega Enterprises, Ltd.
    Inventors: Seisuke Morioka, Keisuke Yasui
  • Patent number: 6172687
    Abstract: A memory device in which a plurality of data can be read out by giving one address and a plurality of data can be read out without adding more address lines is provided, and therefore, the circuit integration is not degraded. The memory device includes: m memory array banks, each including row and column address decoders; a first circuit for receiving one address and generating m row addresses and n column addresses by shifting the one address by a predetermined value for each of the m row and n column addresses; and a second circuit for inputting each of the generated m row and n column addresses to the corresponding row and column address decoders of the m memory array banks.
    Type: Grant
    Filed: March 19, 1998
    Date of Patent: January 9, 2001
    Assignee: Sega Enterprises, Ltd.
    Inventors: Kenya Kitamura, Hiroshi Yagi, Keisuke Yasui
  • Patent number: 6128637
    Abstract: Methods and systems consistent with the present invention provide an arithmetic unit, which uses a high speed yet small circuit, using a highly precise method for numerical interpolation that uses Newton-Raphson method.A table for referencing sampling values and operation results is stored successively and alternately in two simultaneously accessible memories 422, 423. A table reference address determining portion 4211 takes the table reference address from the input B. The access control circuit 4212 prepares an address for accessing each memory from the table reference address and reads table values. The interpolation operating portion 4213 interpolates the table value at a precision of half the final precision. The Newton-Raphson operation 4214 performs the Newton-Raphson operation once with the primary interpolated numerical value as the initial value and attains the calculation results with the final precision by precise square convergence.
    Type: Grant
    Filed: April 6, 1998
    Date of Patent: October 3, 2000
    Assignee: Kabushiki Kaisha Sega Enterprises
    Inventors: Keisuke Yasui, Teruo Okabe
  • Patent number: 6081615
    Abstract: By fixing the area of interpolation or by enlarging it at a ratio smaller than the magnification ratio of texture cells in relation to pixels, to provide an image-processing device and method of image-processing whereby the display image is not subject to excessive fuzziness. CPU 1 determines the display position of objects including texture on the display image. A texture calculator 3 calculates and determines the coordinates of the pixels on the actual display image which correspond to each texture cell. On the basis of these coordinates, a texture interpolator 5 extracts texture data from a texture memory 4, and determines the value of each pixel on the actual display image in accordance with this data. The texture interpolator 5 employs a box filter to determine the interpolation area, but since the size of the box filter is fixed at the same size as that of the pixels which constitute the display image, it does not create any excessive fuzziness on the display image.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: June 27, 2000
    Assignee: Kabushiki Kaisha Sega Enterprises
    Inventor: Keisuke Yasui