Patents by Inventor Keisyun LIN

Keisyun LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10812111
    Abstract: A semiconductor apparatus includes a storage unit, an ECC decoder, and a selection unit. The storage unit stores data. The ECC decoder can detect and correct an error of a predetermined number of bits in data outputted from the storage unit, and can detect an error equal to or larger than bits larger than the predetermined number of bits in the data. The selection unit selects and outputs one of the data outputted from the ECC decoder and a preset fixed value, in accordance with a detection signal indicating whether or not the error equal to or larger than the bits larger than the predetermined number of bits is detected by the ECC decoder.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: October 20, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Keisyun Lin
  • Publication number: 20190288709
    Abstract: A semiconductor apparatus includes a storage unit, an ECC decoder, and a selection unit. The storage unit stores data. The ECC decoder can detect and correct an error of a predetermined number of bits in data outputted from the storage unit, and can detect an error equal to or larger than bits larger than the predetermined number of bits in the data. The selection unit selects and outputs one of the data outputted from the ECC decoder and a preset fixed value, in accordance with a detection signal indicating whether or not the error equal to or larger than the bits larger than the predetermined number of bits is detected by the ECC decoder.
    Type: Application
    Filed: September 4, 2018
    Publication date: September 19, 2019
    Inventor: Keisyun Lin
  • Publication number: 20160372211
    Abstract: An error detection apparatus includes an address generation circuit configured to output an address designating a memory cell unit of a semiconductor memory device to be tested, the memory cell unit including a plurality of memory bits, a test data generation circuit configured to generate test data to be written to the memory cell unit, a control circuit configured to cause the test data to be written to the memory cell unit designated by the address, in synchronization with a cycle of a clock signal, and the written test data to be read from the memory cell unit, in synchronization with the next cycle of the clock signal, and a comparison circuit configured to compare the written test data and the read test data.
    Type: Application
    Filed: March 4, 2016
    Publication date: December 22, 2016
    Inventor: Keisyun LIN