Abstract: A memory device includes a lower source-level semiconductor layer, a source contact layer, and an upper source-level semiconductor layer, an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, the upper source-level semiconductor layer, and the source contact layer, and a memory opening fill structure located in the memory opening and including a memory film and a vertical semiconductor layer having a surface segment that contacts the source contact layer. In one embodiment, the upper source-level semiconductor layer may be locally thickened to provide sufficient etch resistance during formation of a lateral isolation trench. In another embodiment, a sacrificial line trench fill structure may be employed as an etch stop structure during formation of a lateral isolation trench.

Abstract: Word lines are formed from a stack of layers that includes a metal (e.g. tungsten) layer with an overlying multi-layer cap structure. The multi-layer cap structure includes a layer with a low etch rate to protect metal from damage during anisotropic etching. The multi-layer cap structure includes a layer with stress (e.g. tensile) that is opposite to the stress of the metal (e.g. compressive) to provide low combined stress.

Abstract: Word lines are formed from a stack of layers that includes a metal (e.g. tungsten) layer with an overlying multi-layer cap structure. The multi-layer cap structure includes a layer with a low etch rate to protect metal from damage during anisotropic etching. The multi-layer cap structure includes a layer with stress (e.g. tensile) that is opposite to the stress of the metal (e.g. compressive) to provide low combined stress.