Patents by Inventor Keita Masuda

Keita Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105796
    Abstract: A semiconductor device includes an insulating layer, a semiconductor layer and a control electrode. The semiconductor layer is provided on the insulating layer and includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type and a third semiconductor region of a second conductivity type. The third semiconductor region is located between the first semiconductor region and the second semiconductor region. The first to third semiconductor regions are arranged in a first direction along an interface between the insulating layer and the semiconductor layer. The control electrode is provided on the semiconductor layer and includes first to third control parts arranged in the first direction. The first control part is located between the second control part and the third control part. The third semiconductor region is positioned between the insulating layer and the first control part.
    Type: Application
    Filed: March 3, 2023
    Publication date: March 28, 2024
    Inventors: Mitsutoshi NAKAMURA, Masami NAGAOKA, Kazuya NISHIHORI, Keita MASUDA
  • Publication number: 20240080590
    Abstract: Photoelectric conversion apparatus includes read circuit for reading signals of pixel array, and signal processing unit for generating pixel signal by performing CDS on signals read by the read circuit and performing shading correction on the pixel signal. The read circuit has function of reading signal of the pixel array with first and second gain. The read circuit reads noise level with the first gain and reads optical signal level with the first or second gain from selected effective pixel for the correlated double sampling. In the shading correction, pixel signal of effective pixel from which optical signal level has been read with the first gain is corrected based on first correction value, and pixel signal of effective pixel from which optical signal level has been read with the second gain is corrected based on second correction value.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 7, 2024
    Inventors: TAKESHI SHIMADA, KEISUKE TAKAHASHI, KEITA MASUDA, HIDEO KOBAYASHI
  • Publication number: 20240080592
    Abstract: A photoelectric conversion apparatus includes a pixel array having a plurality of column signal lines which are divided into a plurality of groups, a readout circuit configured to read out signals from the pixel array via the plurality of column signal lines. A holding unit includes one first region and a plurality of second regions. A plurality of first correction values respectively corresponding to the plurality of columns are stored in the first region. Each second region is associated with a readout condition for reading signals from each pixel unit of the pixel array by the readout circuit, and a plurality of second correction values respectively corresponding to the plurality of groups are stored in each second region.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 7, 2024
    Inventors: KEITA MASUDA, ATSUSHI SHIMADA, YASUHIRO KATO, KEISUKE TAKAHASHI, TAKESHI SHIMADA
  • Publication number: 20230290876
    Abstract: A semiconductor device includes an insulating layer, a semiconductor layer on the insulating layer, and a control electrode on the semiconductor layer. The semiconductor layer includes first and second semiconductor parts and a separation trench between the first and second semiconductor parts. The first and second semiconductor parts extending along the insulating film. The first semiconductor part includes first and second regions of a first conductivity type, and a fifth region of a second conductivity type between the first and second regions. The second semiconductor part includes third and fourth regions of the second conductivity type, and a sixth region of the second conductivity type between the third and fourth regions. The control electrode extends over the fifth and sixth regions. The semiconductor layer further including a seventh region of the second conductivity type at a bottom of the separation trench and electrically connecting the fifth and sixth regions.
    Type: Application
    Filed: September 1, 2022
    Publication date: September 14, 2023
    Inventors: Mitsutoshi NAKAMURA, Masami NAGAOKA, Kazuya NISHIHORI, Keita MASUDA
  • Patent number: 11715796
    Abstract: A high frequency transistor includes a first semiconductor layer, a first insulating film and a control electrode. The first semiconductor layer on the first insulating film extends in a first direction along an upper surface of the first insulating film. The first semiconductor layer has a first layer thickness in a second direction perpendicular to the upper surface, and a first width in a third direction orthogonal to the first direction. The first width is greater than the first layer thickness. The control electrode covers upper and side surfaces of the first semiconductor layer. The first semiconductor layer includes a first region of a first conductivity type, second and third regions of a second conductivity type. The first to third regions are arranged in the first direction. The first region is provided between the second and third region. The control electrode covers the first region.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: August 1, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Mitsutoshi Nakamura, Kazuya Nishihori, Keita Masuda
  • Publication number: 20220293791
    Abstract: A high frequency transistor includes a first semiconductor layer, a first insulating film and a control electrode. The first semiconductor layer on the first insulating film extends in a first direction along an upper surface of the first insulating film. The first semiconductor layer has a first layer thickness in a second direction perpendicular to the upper surface, and a first width in a third direction orthogonal to the first direction. The first width is greater than the first layer thickness. The control electrode covers upper and side surfaces of the first semiconductor layer. The first semiconductor layer includes a first region of a first conductivity type, second and third regions of a second conductivity type. The first to third regions are arranged in the first direction. The first region is provided between the second and third region. The control electrode covers the first region.
    Type: Application
    Filed: September 10, 2021
    Publication date: September 15, 2022
    Inventors: Mitsutoshi Nakamura, Kazuya Nishihori, Keita Masuda
  • Patent number: 10809511
    Abstract: The total internal reflection microscope has an illumination optical system that relays light from a light source with a relay optical system, forms an image of the light source on the incident pupil plane of the objective lens and irradiates a sample with the illumination light via an objective lens, has an angle adjustment mirror for changing the position of the image of the light source in a direction orthogonal to the optical axis, an optical detector for detecting the intensity of the returning illumination light reflected by the sample and collected by the objective lens, and a controller for determining the operation amount of the angle adjustment mirror, wherein the controller determines the operation amount of the angle adjustment mirror so that the illumination light is totally reflected at the sample based on the change in intensity of the returning light when the angle adjustment mirror is changed.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: October 20, 2020
    Assignee: NIKON CORPORATION
    Inventors: Takayuki Morita, Akitoshi Suzuki, Tomoko Kobayashi, Keita Masuda
  • Patent number: 10593044
    Abstract: An information processing apparatus includes a depth image acquisition unit configured to acquire a depth image from a measurement apparatus that has measured a distance to an object, an image acquisition unit configured to acquire a captured image from an image capturing apparatus that has captured an image of the object, and an estimation unit configured to estimate a shape of the object based on the depth image and the captured image. The estimation unit acquires information about a contour of the object from the captured image, corrects the information about the contour based on the depth image, and estimates the shape of the object based on the corrected information about the contour.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 17, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keita Masuda
  • Patent number: 10347655
    Abstract: A radio frequency switch includes a switch circuit having switchable radio frequency (RF) signal pathways. Each switchable RF signal pathway comprises a plurality of n-type MOSFETs connected in series. A control circuit is configured to control a conduction state of the plurality of switchable RF signal pathways. Each n-type MOSFET includes a body region between a source region thereof and a drain region thereof. A gate electrode is on the body region. A silicon nitride film having a tensile internal stress covers the source layer, the drain layer, and the gate electrode.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: July 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nishihori, Keita Masuda, Tooru Suga, Takahiro Nakagawa, Kazuhiko Shibata
  • Publication number: 20190187449
    Abstract: The total internal reflection microscope has an illumination optical system that relays light from a light source with a relay optical system, forms an image of the light source on the incident pupil plane of the objective lens and irradiates a sample with the illumination light via an objective lens, has an angle adjustment mirror for changing the position of the image of the light source in a direction orthogonal to the optical axis, an optical detector for detecting the intensity of the returning illumination light reflected by the sample and collected by the objective lens, and a controller for determining the operation amount of the angle adjustment mirror, wherein the controller determines the operation amount of the angle adjustment mirror so that the illumination light is totally reflected at the sample based on the change in intensity of the returning light when the angle adjustment mirror is changed.
    Type: Application
    Filed: February 21, 2019
    Publication date: June 20, 2019
    Applicant: NIKON CORPORATION
    Inventors: Takayuki MORITA, Akitoshi SUZUKI, Tomoko KOBAYASHI, Keita MASUDA
  • Patent number: 10241312
    Abstract: The total internal reflection microscope has an illumination optical system that relays light from a light source with a relay optical system, forms an image of the light source on the incident pupil plane of the objective lens and irradiates a sample with the illumination light via an objective lens, has an angle adjustment mirror for changing the position of the image of the light source in a direction orthogonal to the optical axis, an optical detector for detecting the intensity of the returning illumination light reflected by the sample and collected by the objective lens, and a controller for determining the operation amount of the angle adjustment mirror, wherein the controller determines the operation amount of the angle adjustment mirror so that the illumination light is totally reflected at the sample based on the change in intensity of the returning light when the angle adjustment mirror is changed.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: March 26, 2019
    Assignee: NIKON CORPORATION
    Inventors: Takayuki Morita, Akitoshi Suzuki, Tomoko Kobayashi, Keita Masuda
  • Publication number: 20190066306
    Abstract: An information processing apparatus includes a depth image acquisition unit configured to acquire a depth image from a measurement apparatus that has measured a distance to an object, an image acquisition unit configured to acquire a captured image from an image capturing apparatus that has captured an image of the object, and an estimation unit configured to estimate a shape of the object based on the depth image and the captured image. The estimation unit acquires information about a contour of the object from the captured image, corrects the information about the contour based on the depth image, and estimates the shape of the object based on the corrected information about the contour.
    Type: Application
    Filed: August 28, 2018
    Publication date: February 28, 2019
    Inventor: Keita Masuda
  • Publication number: 20170213848
    Abstract: A radio frequency switch includes a switch circuit having switchable radio frequency (RF) signal pathways. Each switchable RF signal pathway comprises a plurality of n-type MOSFETs connected in series. A control circuit is configured to control a conduction state of the plurality of switchable RF signal pathways. Each n-type MOSFET includes a body region between a source region thereof and a drain region thereof. A gate electrode is on the body region. A silicon nitride film having a tensile internal stress covers the source layer, the drain layer, and the gate electrode.
    Type: Application
    Filed: January 19, 2017
    Publication date: July 27, 2017
    Inventors: Kazuya NISHIHORI, Keita MASUDA, Tooru SUGA, Takahiro NAKAGAWA, Kazuhiko SHIBATA
  • Patent number: 9654094
    Abstract: According to one embodiment, a semiconductor switch circuit includes a semiconductor substrate, an insulating film, a semiconductor layer, a first wiring line, a semiconductor switch unit, and a first conductor. The insulating film is provided on the semiconductor substrate. The semiconductor layer is provided on the insulating film. The first wiring line is provided above the insulating film. The semiconductor switch unit is provided on the semiconductor layer and is electrically connected to the first wiring line. The first conductor is provided between the first wiring line and the semiconductor substrate.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: May 16, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Ishimaru, Keita Masuda
  • Publication number: 20160246043
    Abstract: The total internal reflection microscope has an illumination optical system that relays light from a light source with a relay optical system, forms an image of the light source on the incident pupil plane of the objective lens and irradiates a sample with the illumination light via an objective lens, has an angle adjustment mirror for changing the position of the image of the light source in a direction orthogonal to the optical axis, an optical detector for detecting the intensity of the returning illumination light reflected by the sample and collected by the objective lens, and a controller for determining the operation amount of the angle adjustment mirror, wherein the controller determines the operation amount of the angle adjustment mirror so that the illumination light is totally reflected at the sample based on the change in intensity of the returning light when the angle adjustment mirror is changed.
    Type: Application
    Filed: April 29, 2016
    Publication date: August 25, 2016
    Applicant: NIKON CORPORATION
    Inventors: Takayuki MORITA, Akitoshi SUZUKI, Tomoko KOBAYASHI, Keita MASUDA
  • Publication number: 20150263721
    Abstract: According to one embodiment, a semiconductor switch circuit includes a semiconductor substrate, an insulating film, a semiconductor layer, a first wiring line, a semiconductor switch unit, and a first conductor. The insulating film is provided on the semiconductor substrate. The semiconductor layer is provided on the insulating film. The first wiring line is provided above the insulating film. The semiconductor switch unit is provided on the semiconductor layer and is electrically connected to the first wiring line. The first conductor is provided between the first wiring line and the semiconductor substrate.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Atsushi Ishimaru, Keita Masuda
  • Publication number: 20050035431
    Abstract: A semiconductor device includes: a collector region having a first conductivity type; an intrinsic base region having a second conductivity type provided on the collector region; an emitter region having the first conductivity type formed in an upper section of the intrinsic base region; an isolation region provided on a side of the collector region directly under the intrinsic base region; an extrinsic base region having the second conductivity type provided adjacent to the intrinsic base region, and having a higher impurity concentration than the intrinsic base region; and a base electrode region provided on the isolation region, and contacting a side of the extrinsic base region so as to have a region at the same level as the intrinsic base region.
    Type: Application
    Filed: July 8, 2004
    Publication date: February 17, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Keita Masuda
  • Publication number: 20040262714
    Abstract: A semiconductor device includes: a collector region of first conductive type formed on a semiconductor substrate; a base region of second conductive type formed on the collector region of first conductive type; a non-doped layer forming region formed in part of a surface region of the base region of second conductive type; an emitter region of first conductive type formed in the non-doped layer forming region so that a bottom of the emitter region reaches the base region of second conductive type; a base leading-out region of second conductive type formed on the base region of second conductive type; a dielectric formed on an upper portion and a side portion of the base leading-out region of second conductive type and the non-doped layer forming region; and an emitter leading-out region of first conductive type formed on the emitter region of first conductive type.
    Type: Application
    Filed: March 31, 2004
    Publication date: December 30, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Noda, Keita Masuda