Patents by Inventor Keita Matsuda
Keita Matsuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230411315Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor element formed on the semiconductor substrate, a first insulating film covering the semiconductor element, a second insulating film formed on the first insulating film, and a third insulating film formed on the second insulating film. The first and third insulating films allow less moisture to pass than the second insulating film. A dielectric constant of the second insulating film is lower than dielectric constants of the first and third insulating films. The first insulating film has a first portion that is in contact with a first region of an upper surface of the semiconductor substrate. The third insulating film has a second portion that is in contact with upper and side surfaces of the first portion and a second region of the upper surface. The second region is farther away from the semiconductor element than the first region.Type: ApplicationFiled: March 2, 2023Publication date: December 21, 2023Inventor: Keita MATSUDA
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Patent number: 11594507Abstract: A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.Type: GrantFiled: April 22, 2021Date of Patent: February 28, 2023Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita Matsuda
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Publication number: 20220389229Abstract: Provided is a method for effectively modifying a surface of a h-BN particle including a (0001) plane, which is a base surface of h-BN, with a variety of materials. A method for producing a surface-coated hexagonal boron nitride particle of one embodiment includes mixing a hexagonal boron nitride particle (a), a coupling agent (b), and a catalyst (c) having a polar group and an aromatic ring in a solvent to form a layer containing a condensate of the coupling agent on at least a portion of a surface of the hexagonal boron nitride particle.Type: ApplicationFiled: May 25, 2022Publication date: December 8, 2022Inventors: Keita Matsuda, Taiki Ihara, Ricardo Gorgoll
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Patent number: 11270967Abstract: There is provided a method for manufacturing a semiconductor device comprising: forming a first organic insulating layer on a semiconductor region; forming a bump base film including an edge portion contacting with the first organic insulating layer; performing heat treatment of the bump base film; and forming a second organic insulating layer so as to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film while contacting with the first organic insulating layer, the second organic insulating layer being provided with a first opening that exposes a surface of the bump base film.Type: GrantFiled: February 25, 2020Date of Patent: March 8, 2022Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita Matsuda
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Publication number: 20210351147Abstract: A method for manufacturing a semiconductor device includes forming a thermosetting resin film on a first metal layer, forming an opening in the resin film, forming a second metal layer that covers a region from an upper surface of the first metal layer exposed from the opening of the resin film to an upper surface of the resin film, performing heat treatment at a temperature equal to or higher than a temperature at which the resin film is cured after forming the second metal layer, forming a cover film that covers the upper surface of the resin film and a side surface of the second metal layer after performing the heat treatment, and forming a solder on an upper surface of the second metal layer exposed from an opening of the cover film after forming the cover film.Type: ApplicationFiled: April 22, 2021Publication date: November 11, 2021Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita MATSUDA
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Patent number: 11056451Abstract: A semiconductor device manufacturing method includes forming an organic insulating layer on a semiconductor on which metal wiring is provided, the organic insulating layer having an opening to expose part of the metal wiring, forming a seed metal covering the part of the metal wiring exposed from the opening, and an inside face and an around portion of the opening of the organic insulating layer, forming a mask covering an edge of the seed metal and exposing part of the seed metal formed in the opening, and forming a barrier metal on the seed metal exposed from the mask by electroless plating. The mask includes an organic material or an inorganic dielectric material.Type: GrantFiled: September 12, 2019Date of Patent: July 6, 2021Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita Matsuda
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Publication number: 20210091023Abstract: A semiconductor device is made by a manufacturing method that includes forming an organic insulating layer on a semiconductor on which metal wiring is provided, the organic insulating layer having an opening to expose part of the metal wiring, forming a seed metal covering the part of the metal wiring exposed from the opening, and an inside face and an around portion of the opening of the organic insulating layer, forming a mask covering an edge of the seed metal and exposing part of the seed metal formed in the opening, and forming a barrier metal on the seed metal exposed from the mask by electroless plating. The mask includes an organic material or an inorganic dielectric material.Type: ApplicationFiled: November 18, 2020Publication date: March 25, 2021Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita MATSUDA
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Publication number: 20200279822Abstract: There is provided a method for manufacturing a semiconductor device comprising: forming a first organic insulating layer on a semiconductor region; forming a bump base film including an edge portion contacting with the first organic insulating layer; performing heat treatment of the bump base film; and forming a second organic insulating layer so as to cover the edge portion of the bump base film and the first organic insulating layer around the bump base film while contacting with the first organic insulating layer, the second organic insulating layer being provided with a first opening that exposes a surface of the bump base film.Type: ApplicationFiled: February 25, 2020Publication date: September 3, 2020Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita MATSUDA
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Publication number: 20200091098Abstract: A semiconductor device manufacturing method includes forming an organic insulating layer on a semiconductor on which metal wiring is provided, the organic insulating layer having an opening to expose part of the metal wiring, forming a seed metal covering the part of the metal wiring exposed from the opening, and an inside face and an around portion of the opening of the organic insulating layer, forming a mask covering an edge of the seed metal and exposing part of the seed metal formed in the opening, and forming a barrier metal on the seed metal exposed from the mask by electroless plating. The mask includes an organic material or an inorganic dielectric material.Type: ApplicationFiled: September 12, 2019Publication date: March 19, 2020Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita Matsuda
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Patent number: 10283472Abstract: A semiconductor device of the ball grid array (BGA) type, the device having an electrode, and a process of forming the electrode are disclosed. The electrode includes an insulating film, a seed layer on the insulating film, a mound metal on the insulating film and an interconnection on the seed layer. The mound metal surrounds the seed layer without forming any gap therebetween. The interconnection, which is formed by electroless plating, is apart from the insulating film with the mound metal as an extension barrier for the plating.Type: GrantFiled: June 19, 2017Date of Patent: May 7, 2019Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita Matsuda
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Publication number: 20170365571Abstract: A semiconductor device having an electrode type of the ball grid array (BGA) and a process of forming the electrode are disclosed. The electrode insulating film, a seed layer on the insulating film, a mound metal on the insulating film and an interconnection on the seed layer. The mound metal surrounds the seed layer without forming any gap therebetween. The interconnection, which is formed by electroless plating, is apart from the insulating film with the mound metal as an extension barrier for the plating.Type: ApplicationFiled: June 19, 2017Publication date: December 21, 2017Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Keita MATSUDA
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Patent number: 8846520Abstract: A semiconductor device includes: a foundation layer that is provided on a substrate and is electrically conductive; a nickel layer provided on the foundation layer; and a solder provided on the nickel layer, the nickel layer having a first region on a side of the foundation layer and a second region on a side of the solder, the second region being harder than the first region.Type: GrantFiled: September 28, 2012Date of Patent: September 30, 2014Assignee: Sumitomo Electric Device Innovations, Inc.Inventor: Keita Matsuda
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Publication number: 20110217816Abstract: A field effect transistor includes: a nitride semiconductor layer having a channel layer; a gate electrode including a Schottky electrode that contacts the nitride semiconductor layer and includes a gallium doped zinc oxide (GZO) layer annealed in an inactive gas atmosphere; and ohmic electrodes connecting with the channel layer.Type: ApplicationFiled: May 18, 2011Publication date: September 8, 2011Applicant: EUDYNA DEVICES INC.Inventor: Keita MATSUDA
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Patent number: 7875538Abstract: A semiconductor device includes: a nitride semiconductor layer including a channel layer, a Schottky electrode that contacts the nitride semiconductor layer and contains indium, and an ohmic electrode that contacts the channel layer. The nitride semiconductor layer includes a layer that contacts the Schottky electrode and contains AlGaN, InAlGaN or GaN. The Schottky electrode that contains indium includes one of an indium oxide layer and an indium tin oxide layer.Type: GrantFiled: November 26, 2007Date of Patent: January 25, 2011Assignee: Eudyna Devices Inc.Inventor: Keita Matsuda
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Publication number: 20090026498Abstract: A field effect transistor includes: a nitride semiconductor layer having a channel layer; a gate electrode including a Schottky electrode that contacts the nitride semiconductor layer and includes a gallium doped zinc oxide (GZO) layer annealed in an inactive gas atmosphere; and ohmic electrodes connecting with the channel layer.Type: ApplicationFiled: July 25, 2008Publication date: January 29, 2009Applicant: EUDYNA DEVICES INC.Inventor: Keita MATSUDA
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Publication number: 20080121934Abstract: A semiconductor device includes: a nitride semiconductor layer including a channel layer, a Schottky electrode that contacts the nitride semiconductor layer and contains indium, and an ohmic electrode that contacts the channel layer. The nitride semiconductor layer includes a layer that contacts the Schottky electrode and contains AlGaN, InAlGaN or GaN. The Schottky electrode that contains indium includes one of an indium oxide layer and an indium tin oxide layer.Type: ApplicationFiled: November 26, 2007Publication date: May 29, 2008Applicant: EUDYNA DEVICES INC.Inventor: Keita MATSUDA
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Patent number: 5945811Abstract: The present invention relates to a pulse charging method and charging system for use with non-aqueous secondary batteries, employing a pulse charge controlling method all the way from the start to the end of charging. This pulse charging method has an on-duty ratio of pulses in a next specified charge period reduced when an average battery voltage has exceeded a charge control voltage during a specified charge period, has an on-duty ratio of pulses in a next specified charge period increased when the average battery voltage has not exceeded the charge control voltage and has the pulse charging ended when an on-duty ratio of pulses has reached a specified value. The pulse charging system comprises an on-duty ratio reducing means for having an on-duty ratio of pulses reduced, an on-duty ratio increasing means for having an on-duty ratio increased and a means for determining pulse charge ending for having the pulse charging ended when an on-duty ratio of pulses has reached a specified value.Type: GrantFiled: January 21, 1998Date of Patent: August 31, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hirokazu Hasegawa, Yasutaka Iwao, Keita Matsuda, Akihide Konno