Patents by Inventor Keita MURASE

Keita MURASE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11968466
    Abstract: A solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus are provided that are capable of reducing memory circuits of a column reading system, so that the column reading system can achieve a reduced layout area and eventually a reduced size. A column reading circuit includes an AD converting part and a calculating part. The AD converting part is configured to analog-to-digital convert a read-out reset signal and a read-out signal of a pixel signal read to a vertical signal line into an n-bit digital pixel signal. The calculating part includes an n-bit asynchronous counter including a retention circuit with a control logic function, which is configured to obtain a difference between an n-bit read-out reset signal and an n-bit read-out signal produced by the AD conversion performed by the AD converting part.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: April 23, 2024
    Assignee: BRILLNICS SINGAPORE PTE. LTD.
    Inventors: Naoyuki Abe, Keita Murase, Takahiro Matsuzawa, Shinichiro Matsuo, Shingo Sanada
  • Publication number: 20230038227
    Abstract: A solid-state imaging device, a method for driving a solid-state imaging device, and an electronic apparatus are provided that are capable of reducing memory circuits of a column reading system, so that the column reading system can achieve a reduced layout area and eventually a reduced size. A column reading circuit includes an AD converting part and a calculating part. The AD converting part is configured to analog-to-digital convert a read-out reset signal and a read-out signal of a pixel signal read to a vertical signal line into an n-bit digital pixel signal. The calculating part includes an n-bit asynchronous counter including a retention circuit with a control logic function, which is configured to obtain a difference between an n-bit read-out reset signal and an n-bit read-out signal produced by the AD conversion performed by the AD converting part.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 9, 2023
    Inventors: Naoyuki ABE, Keita MURASE, Takahiro MATSUZAWA, Shinichiro MATSUO, Shingo SANADA
  • Patent number: 11428548
    Abstract: A capacitance measuring circuit measures an electrostatic capacitance formed between a first conductor that receive an AC signal and a second conductor. The capacitance measuring circuit includes an amplifier including an input and an output; signal detection means including a negative feedback unit that has a feedback capacitance and applies a negative feedback from an output of the amplifier to an input of the amplifier, wherein an input of the amplifier is connected to the second conductor and is virtually grounded by the negative feedback unit and an AC signal of an amplitude in a functional relation with the electrostatic capacitance is output; and measuring means that is connected to an output of the signal detection means and has a function of measuring at least an amplitude of an AC signal output of the signal detection means.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: August 30, 2022
    Assignee: NF HOLDINGS CORPORATION
    Inventors: Shingo Sobukawa, Keita Murase, Takehito Kamimura
  • Publication number: 20210072048
    Abstract: A capacitance measuring circuit measures an electrostatic capacitance formed between a first conductor that receive an AC signal and a second conductor. The capacitance measuring circuit includes an amplifier including an input and an output; signal detection means including a negative feedback unit that has a feedback capacitance and applies a negative feedback from an output of the amplifier to an input of the amplifier, wherein an input of the amplifier is connected to the second conductor and is virtually grounded by the negative feedback unit and an AC signal of an amplitude in a functional relation with the electrostatic capacitance is output; and measuring means that is connected to an output of the signal detection means and has a function of measuring at least an amplitude of an AC signal output of the signal detection means.
    Type: Application
    Filed: October 28, 2020
    Publication date: March 11, 2021
    Inventors: Shingo SOBUKAWA, Keita MURASE, Takehito KAMIMURA