Patents by Inventor Keita Takada
Keita Takada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230402443Abstract: A semiconductor device includes: a first chip mounting portion; a second chip mounting portion; a first semiconductor chip mounted on the first chip mounting portion; second and third semiconductor chips mounted on the second chip mounting portion; and a sealing body for sealing them. Here, the third semiconductor chip includes a first coil and a second coil that are magnetically coupled to each other. Also, the first coil is electrically connected with a first circuit formed in the first semiconductor chip, and the second coil is electrically connected with a second circuit formed in the second semiconductor chip. Also, in cross-sectional view, the second coil is located closer to the second chip mounting portion than the first coil. Further, a power consumption during an operation of the second semiconductor chip is greater than a power consumption during an operation of the first semiconductor chip.Type: ApplicationFiled: April 20, 2023Publication date: December 14, 2023Inventors: Yoshihiro MASUMURA, Takamichi HOSOKAWA, Keita TAKADA
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Publication number: 20230378032Abstract: To manufacture a semiconductor device, a first heat treatment for curing a first adhesive material of a conductive paste type is performed, after a semiconductor chip is mounted on a die pad of a lead frame via the first adhesive material. After that, a metal plate is disposed on a pad of the semiconductor chip such that the metal plate faces the pad of the semiconductor chip via a second adhesive material of a conductive paste type, and a second heat treatment is performed for curing each of the first adhesive material and the second adhesive material. A time of the first heat treatment is less than a time of the second heat treatment. After the first adhesive material is cured by the first heat treatment, the first adhesive material is further cured by the second heat treatment.Type: ApplicationFiled: February 28, 2023Publication date: November 23, 2023Inventors: Kosuke KITAICHI, Masatoshi SUGIURA, Hideaki TAMIMOTO, Takehiko MAEDA, Keita TAKADA, Yoshitaka KYOUGOKU
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Patent number: 10811281Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.Type: GrantFiled: June 26, 2019Date of Patent: October 20, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shoji Hashizume, Keita Takada
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Publication number: 20190318939Abstract: A manufacturing method of a semiconductor device, includes: (a) preparing a lead frame having: a first tie bar extending in a first direction in plan view so as to couple a plurality of first leads to one another; a second tie bar extending in the first direction in plan view so as to couple a plurality of second leads to one another; a coupling portion coupled to the first tie bar and the second tie bar; a first chip mounting portion arranged between the first tie bar and the second tie bar in plan view; and a second chip mounting portion arranged between the first chip mounting portion and the second tie bar in plan view; and (b) after the (a), mounting a first semiconductor chip on the first chip mounting portion and mounting a second semiconductor chip on the second chip mounting portion.Type: ApplicationFiled: June 26, 2019Publication date: October 17, 2019Inventors: Shoji HASHIZUME, Keita Takada
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Patent number: 10403513Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.Type: GrantFiled: February 20, 2018Date of Patent: September 3, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shoji Hashizume, Keita Takada
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Publication number: 20180306844Abstract: A power MOSFET and a sense MOSFET for detecting a current of the power MOSFET are formed in a semiconductor chip, and a source pad and a Kelvin pad are formed of a source electrode for the power MOSFET. The source pad is a pad for outputting the current flowing to the power MOSFET, and the Kelvin pad is a pad for detecting a source potential of the power MOSFET. The source electrode has a slit, and at least a part of the slit is arranged between the source pad and the Kelvin pad when seen in a plan view.Type: ApplicationFiled: June 26, 2018Publication date: October 25, 2018Inventors: Keita TAKADA, Nobuya KOIKE, Akihiro NAKAHARA, Makoto TANAKA
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Patent number: 10109565Abstract: Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.Type: GrantFiled: December 15, 2016Date of Patent: October 23, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Keita Takada, Tadatoshi Danno
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Publication number: 20180277397Abstract: In a manufacturing method of a semiconductor device, by arranging a lead in the vicinity of a gate portion serving as a resin injection port of a mold, a void is prevented from remaining within an encapsulation body when two semiconductor chips arranged so as to overlap in the Y direction are encapsulated with resin. Further, a length of an inner lead portion of the lead in the Y direction is greater than a length of an inner lead portion of another lead overlapping a chip mounting portion in the Y direction.Type: ApplicationFiled: February 20, 2018Publication date: September 27, 2018Inventors: Shoji HASHIZUME, Keita TAKADA
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Patent number: 10031164Abstract: A power MOSFET and a sense MOSFET for detecting a current of the power MOSFET are formed in a semiconductor chip, and a source pad and a Kelvin pad are formed of a source electrode for the power MOSFET. The source pad is a pad for outputting the current flowing to the power MOSFET, and the Kelvin pad is a pad for detecting a source potential of the power MOSFET. The source electrode has a slit, and at least a part of the slit is arranged between the source pad and the Kelvin pad when seen in a plan view.Type: GrantFiled: September 21, 2016Date of Patent: July 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Keita Takada, Nobuya Koike, Akihiro Nakahara, Makoto Tanaka
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Patent number: 9922905Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: GrantFiled: February 28, 2017Date of Patent: March 20, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Yato, Hiroi Oka, Noriko Okunishi, Keita Takada
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Publication number: 20170179010Abstract: Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.Type: ApplicationFiled: December 15, 2016Publication date: June 22, 2017Inventors: Keita TAKADA, Tadatoshi DANNO
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Publication number: 20170170100Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: ApplicationFiled: February 28, 2017Publication date: June 15, 2017Inventors: Yuichi YATO, Hiroi OKA, Noriko OKUNISHI, Keita TAKADA
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Publication number: 20170089957Abstract: A power MOSFET and a sense MOSFET for detecting a current of the power MOSFET are formed in a semiconductor chip, and a source pad and a Kelvin pad are formed of a source electrode for the power MOSFET. The source pad is a pad for outputting the current flowing to the power MOSFET, and the Kelvin pad is a pad for detecting a source potential of the power MOSFET. The source electrode has a slit, and at least a part of the slit is arranged between the source pad and the Kelvin pad when seen in a plan view.Type: ApplicationFiled: September 21, 2016Publication date: March 30, 2017Inventors: Keita TAKADA, Nobuya KOIKE, Akihiro NAKAHARA, Makoto TANAKA
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Patent number: 9607940Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: GrantFiled: July 5, 2013Date of Patent: March 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichi Yato, Hiroi Oka, Noriko Okunishi, Keita Takada
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Publication number: 20160204057Abstract: A semiconductor device according to an embodiment is a semiconductor device in which a semiconductor chip mounted on a chip mounting part is sealed by resin and a first member is fixed to a chip mounting surface side between a peripheral portion of the semiconductor chip and a peripheral portion of the chip mounting part. Also, the first member is sealed by the resin. Also, a length of the first part of the chip mounting part in the first direction is larger than a length of the semiconductor chip in the first direction, in a plan view.Type: ApplicationFiled: July 5, 2013Publication date: July 14, 2016Inventors: Yuichi YATO, Hiroi OKA, Noriko OKUNISHI, Keita TAKADA
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Publication number: 20160133549Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.Type: ApplicationFiled: December 28, 2015Publication date: May 12, 2016Inventors: Keita TAKADA, Tadatoshi DANNO, Hirokazu KATO
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Patent number: 9252088Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.Type: GrantFiled: November 12, 2014Date of Patent: February 2, 2016Assignee: Renesas Electronics CorporationInventors: Keita Takada, Tadatoshi Danno, Hirokazu Kato
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Publication number: 20150206830Abstract: A lead frame having a first chip-mounting part on which a first semiconductor chip is mounted and having a second chip-mounting part on which a second semiconductor chip is mounted is prepared. Moreover, a process is provided, the process connecting a first electrode pad, which is formed on a top surface of the first semiconductor chip, with a first end of a first metal ribbon and connecting a ribbon-connecting surface on the second chip-mounting part with a second end of the first metal ribbon on the opposite side of the first end. Moreover, in a plan view, the ribbon-connecting surface of the second chip-mounting part is positioned between the first semiconductor chip and the second semiconductor chip. Moreover, the height of the ribbon-connecting surface is positioned at a position higher than the height of a mounting surface of the second semiconductor chip of the second chip-mounting part.Type: ApplicationFiled: September 24, 2012Publication date: July 23, 2015Inventors: Keita Takada, Tadatoshi Danno, Toshiyuki Hata
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Publication number: 20150069594Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.Type: ApplicationFiled: November 12, 2014Publication date: March 12, 2015Inventors: Keita TAKADA, Tadatoshi DANNO, Hirokazu KATO
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Patent number: 8912640Abstract: A semiconductor device is inhibited from being degraded in reliability. The semiconductor device has a tab including a top surface, a bottom surface, and a plurality of side surfaces. Each of the side surfaces of the tab has a first portion continued to the bottom surface of the tab, a second portion located outwardly of the first portion and continued to the top surface of the tab, and a third portion located outwardly of the second portion and continued to the top surface of the tab to face the same direction as each of the first and second portions. In planar view, the outer edge of the semiconductor chip is located between the third portion and the second portion of the tab, and the outer edge of an adhesive material fixing the semiconductor chip to the tab is located between the semiconductor chip and the second portion.Type: GrantFiled: July 2, 2012Date of Patent: December 16, 2014Assignee: Renesas Electronics CorporationInventors: Keita Takada, Tadatoshi Danno, Hirokazu Kato