Patents by Inventor Keita Torii

Keita Torii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11728441
    Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer, and a structure provided between the first and second semiconductor layers. The semiconductor apparatus further includes a first electrode supported by a first insulating layer, a second electrode supported by a second insulating layer, a first wire bonded to the first electrode through a first opening provided in the first semiconductor layer, and a second wire bonded to the second electrode through a second opening provided in the first semiconductor layer, and an annular member made of a non-insulating material and provided between the first semiconductor layer and the first electrode. A distance from the second semiconductor layer to a first joint between the first electrode and the first wire is longer than a distance from the second semiconductor layer to a second joint between the second electrode and the second wire.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 15, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideki Hayashi, Junji Iwata, Keita Torii, Yusuke Todo
  • Patent number: 11682688
    Abstract: A photoelectric converting device including: a semiconductor layer with a front surface and a back surface, the semiconductor layer including a photoelectric conversion portion; a wire structure including an insulating film, the wire structure being disposed on the front surface of the semiconductor layer; a first insulator portion disposed in a trench provided in the semiconductor layer; and a second insulator portion disposed between the first insulator portion and the insulating film, wherein the first insulator portion has a maximum width larger than a maximum width of the second insulator portion.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: June 20, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keita Torii, Hideki Ina
  • Publication number: 20230115792
    Abstract: A photoelectric conversion device includes a substrate, a photoelectric conversion unit arranged in the substrate and configured to generate charges corresponding to incident light, and a pixel isolation portion arranged in the substrate and isolating the photoelectric conversion unit from other elements. A sidewall of the pixel isolation portion has a plurality of depressions and protrusions in a cross-sectional view. A period of at least a part of the plurality of depressions and protrusions is greater than ½ of a wavelength of light to which the photoelectric conversion unit has sensitivity.
    Type: Application
    Filed: September 16, 2022
    Publication date: April 13, 2023
    Inventors: Yu Maehashi, Keita Torii, Takayuki Suzuki, Junji Iwata
  • Publication number: 20210305439
    Abstract: A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer, and a structure provided between the first and second semiconductor layers. The semiconductor apparatus further includes a first electrode supported by a first insulating layer, a second electrode supported by a second insulating layer, a first wire bonded to the first electrode through a first opening provided in the first semiconductor layer, and a second wire bonded to the second electrode through a second opening provided in the first semiconductor layer, and an annular member made of a non-insulating material and provided between the first semiconductor layer and the first electrode. A distance from the second semiconductor layer to a first joint between the first electrode and the first wire is longer than a distance from the second semiconductor layer to a second joint between the second electrode and the second wire.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 30, 2021
    Inventors: Hideki Hayashi, Junji Iwata, Keita Torii, Yusuke Todo
  • Patent number: 11121160
    Abstract: Photoelectric conversion apparatus includes semiconductor layer having photoelectric converters in light-receiving region and photoelectric converters in light-shielded region, light-shielding part arranged above the semiconductor layer in the light-receiving region to surround light paths of the photoelectric converters in the light-receiving region, and light-shielding film arranged above the semiconductor layer in the light-shielded region to cover the photoelectric converters in the light-shielded region. The light-shielding part includes lower and upper ends. The light-shielding film includes lower and upper surfaces. Distance between the upper end and the semiconductor layer is larger than that between the upper surface and the semiconductor layer. Distance between the lower end and the semiconductor layer is smaller than that between the upper surface and the semiconductor layer and is larger than that between the lower surface and the semiconductor layer.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: September 14, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Sho Suzuki, Takehito Okabe, Mitsuhiro Yomori, Takuya Hara, Keita Torii, Yukinobu Suzuki, Tomoyuki Tezuka, Norihiko Nakata, Daichi Seto, Kenji Togo
  • Publication number: 20210118924
    Abstract: A photoelectric conversion device in the present disclosure includes a first trench extending inside a semiconductor substrate from a first face of the semiconductor substrate between a first photoelectric conversion portion and a second photoelectric conversion portion arranged in a first pixel and a second trench extending from a second face of the semiconductor substrate between the first pixel and a second pixel, and the end on the second face side of the first isolation portion is located closer to the second face side than the end on the first face side of the second isolation portion.
    Type: Application
    Filed: October 1, 2020
    Publication date: April 22, 2021
    Inventors: Junya Tamaki, Keita Torii, Kazuya Igarashi
  • Patent number: 10651230
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises forming a first insulator above the substrate, forming a second insulator on the first insulator, performing a first etching process of etching the second insulator by fluorine and hydrogen contained gas to expose the first insulator while leaving a portion of the second insulator which covers a side face of the gate electrode and performing a second etching process of etching a portion of the first insulator exposed by the first etching process. The first etching process includes a first process and a second process performed after the first process. A reaction product is less deposited in the first process than in the second process and etching selectivity of the second insulator with respect to the first insulator is higher in the second process than in the first process.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: May 12, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Keita Torii, Takashi Usui, Takuji Mukai
  • Publication number: 20200135793
    Abstract: A photoelectric converting device including: a semiconductor layer with a front surface and a back surface, the semiconductor layer including a photoelectric conversion portion; a wire structure including an insulating film, the wire structure being disposed on the front surface of the semiconductor layer; a first insulator portion disposed in a trench provided in the semiconductor layer; and a second insulator portion disposed between the first insulator portion and the insulating film, wherein the first insulator portion has a maximum width larger than a maximum width of the second insulator portion.
    Type: Application
    Filed: October 22, 2019
    Publication date: April 30, 2020
    Inventors: Keita Torii, Hideki Ina
  • Publication number: 20200127031
    Abstract: Photoelectric conversion apparatus includes semiconductor layer having photoelectric converters in light-receiving region and photoelectric converters in light-shielded region, light-shielding part arranged above the semiconductor layer in the light-receiving region to surround light paths of the photoelectric converters in the light-receiving region, and light-shielding film arranged above the semiconductor layer in the light-shielded region to cover the photoelectric converters in the light-shielded region. The light-shielding part includes lower and upper ends. The light-shielding film includes lower and upper surfaces. Distance between the upper end and the semiconductor layer is larger than that between the upper surface and the semiconductor layer. Distance between the lower end and the semiconductor layer is smaller than that between the upper surface and the semiconductor layer and is larger than that between the lower surface and the semiconductor layer.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 23, 2020
    Inventors: Sho Suzuki, Takehito Okabe, Mitsuhiro Yomori, Takuya Hara, Keita Torii, Yukinobu Suzuki, Tomoyuki Tezuka, Norihiko Nakata, Daichi Seto, Kenji Togo
  • Patent number: 10403667
    Abstract: A photoelectric conversion device includes a waveguide member disposed above a photoelectric conversion unit, and an insulating member disposed above a substrate, and surrounding at least part of the waveguide member. The waveguide member has a first side face, a second side face, and a third side face, arranged in that order from the substrate. An angle of inclination of the first side face is smaller than an angle of inclination of the second side face. An angle of inclination of the third side face is smaller than the angle of inclination of the second side face. The angle of inclination of the second side face is smaller than 90 degrees.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: September 3, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takashi Usui, Keita Torii, Yusuke Onuki, Hideki Ina
  • Publication number: 20180366512
    Abstract: A method of manufacturing a semiconductor device is provided. The method comprises forming a first insulator above the substrate, forming a second insulator on the first insulator, performing a first etching process of etching the second insulator by fluorine and hydrogen contained gas to expose the first insulator while leaving a portion of the second insulator which covers a side face of the gate electrode and performing a second etching process of etching a portion of the first insulator exposed by the first etching process. The first etching process includes a first process and a second process performed after the first process. A reaction product is less deposited in the first process than in the second process and etching selectivity of the second insulator with respect to the first insulator is higher in the second process than in the first process.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 20, 2018
    Inventors: Keita Torii, Takashi Usui, Takuji Mukai
  • Patent number: 10026774
    Abstract: A method of manufacturing a solid-state image sensor including preparing a wafer including a pixel region where a photoelectric conversion element is provided, a peripheral circuit region where a gate electrode of a peripheral MOS transistor for constituting a peripheral circuit is provided, and a scribe region. The method includes forming an insulating film covering the pixel region, the peripheral circuit region, and the scribe region, and forming a sidewall spacer on a side surface of the gate electrode by etching the insulating film so that portions of the insulating film remains to cover the pixel region and the scribe region, and forming a metal silicide layer in the peripheral circuit region by using, as a mask for protection from silicidation, the insulating film covering the pixel region and the scribe region.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: July 17, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yusuke Onuki, Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Takumi Ogino, Keita Torii
  • Publication number: 20180012921
    Abstract: A photoelectric conversion device includes a waveguide member disposed above a photoelectric conversion unit, and an insulating member disposed above a substrate, and surrounding at least part of the waveguide member. The waveguide member has a first side face, a second side face, and a third side face, arranged in that order from the substrate. An angle of inclination of the first side face is smaller than an angle of inclination of the second side face. An angle of inclination of the third side face is smaller than the angle of inclination of the second side face. The angle of inclination of the second side face is smaller than 90 degrees.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 11, 2018
    Inventors: Takashi Usui, Keita Torii, Yusuke Onuki, Hideki Ina
  • Patent number: 9716126
    Abstract: A method of manufacturing a solid-state image sensor includes forming a first element isolation and a first active region of a pixel area, and a second isolation and a second active region of a peripheral circuit area, forming a gate electrode film covering the first element isolation, the first active region, the second element isolation and the second active region, implanting an n-type impurity selectively into at least a part of the gate electrode film corresponding to the pixel area, and forming, after the implanting of the n-type impurity, a first gate electrode of the pixel area and a second gate electrode of the peripheral circuit area by patterning the gate electrode film. The part of the gate electrode film includes a portion located above a boundary between the first element isolation and the first active region.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: July 25, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Yusuke Onuki, Takumi Ogino, Keita Torii
  • Patent number: 9559136
    Abstract: A semiconductor device manufacturing method includes a step of forming a hole reaching a first insulating layer over a first conductive member; a step of forming a trench reaching a second insulating layer and in communication with the hole; a step of forming an opening exposing the first conductive member in the hole; and a step of forming a second conductive member connected to the first conductive member by embedding a conductive material in the opening, the hole, and the trench. The trench is formed under an etching condition such that the etching rate with respect to the second insulating layer is lower than the etching rate with respect to the third insulating layer.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: January 31, 2017
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aiko Kato, Yu Nishimura, Hiroaki Naruse, Keita Torii
  • Patent number: 9466485
    Abstract: A conductor pattern forming method includes forming, on a conductor film, a laminated film including a first layer thinner than the conductor film, a second layer thicker than the first layer, and a third layer thinner than the second layer, which layers are laminated in order from the conductor film side. A first mask is formed from the third layer by dry-etching the third layer using a photoresist mask formed on the laminated film. A second mask is formed from the second layer by dry-etching the second layer using the first mask. The conductor film is exposed by dry-etching the first layer using the second mask. A conductor pattern is formed from the conductor film by dry-etching the conductor film using the second mask.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: October 11, 2016
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keita Torii
  • Publication number: 20150364522
    Abstract: A method of manufacturing a solid-state image sensor includes forming a first element isolation and a first active region of a pixel area, and a second isolation and a second active region of a peripheral circuit area, forming a gate electrode film covering the first element isolation, the first active region, the second element isolation and the second active region, implanting an n-type impurity selectively into at least a part of the gate electrode film corresponding to the pixel area, and forming, after the implanting of the n-type impurity, a first gate electrode of the pixel area and a second gate electrode of the peripheral circuit area by patterning the gate electrode film. The part of the gate electrode film includes a portion located above a boundary between the first element isolation and the first active region.
    Type: Application
    Filed: June 1, 2015
    Publication date: December 17, 2015
    Inventors: Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Yusuke Onuki, Takumi Ogino, Keita Torii
  • Publication number: 20150364517
    Abstract: A method of manufacturing a solid-state image sensor including preparing a wafer including a pixel region where a photoelectric conversion element is provided, a peripheral circuit region where a gate electrode of a peripheral MOS transistor for constituting a peripheral circuit is provided, and a scribe region. The method includes forming an insulating film covering the pixel region, the peripheral circuit region, and the scribe region, and forming a sidewall spacer on a side surface of the gate electrode by etching the insulating film so that portions of the insulating film remains to cover the pixel region and the scribe region, and forming a metal silicide layer in the peripheral circuit region by using, as a mask for protection from silicidation, the insulating film covering the pixel region and the scribe region.
    Type: Application
    Filed: May 27, 2015
    Publication date: December 17, 2015
    Inventors: Yusuke Onuki, Masatsugu Itahashi, Nobuaki Kakinuma, Mineo Shimotsusa, Masato Fujita, Takumi Ogino, Keita Torii
  • Publication number: 20150228683
    Abstract: A semiconductor device manufacturing method includes a step of forming a hole reaching a first insulating layer over a first conductive member; a step of forming a trench reaching a second insulating layer and in communication with the hole; a step of forming an opening exposing the first conductive member in the hole; and a step of forming a second conductive member connected to the first conductive member by embedding a conductive material in the opening, the hole, and the trench. The trench is formed under an etching condition such that the etching rate with respect to the second insulating layer is lower than the etching rate with respect to the third insulating layer.
    Type: Application
    Filed: February 10, 2015
    Publication date: August 13, 2015
    Inventors: Aiko Kato, Yu Nishimura, Hiroaki Naruse, Keita Torii
  • Publication number: 20150162375
    Abstract: A conductor pattern forming method includes forming, on a conductor film, a laminated film including a first layer thinner than the conductor film, a second layer thicker than the first layer, and a third layer thinner than the second layer, which layers are laminated in order from the conductor film side. A first mask is formed from the third layer by dry-etching the third layer using a photoresist mask formed on the laminated film. A second mask is formed from the second layer by dry-etching the second layer using the first mask. The conductor film is exposed by dry-etching the first layer using the second mask. A conductor pattern is formed from the conductor film by dry-etching the conductor film using the second mask.
    Type: Application
    Filed: December 9, 2014
    Publication date: June 11, 2015
    Inventor: Keita Torii