Abstract: An image processing apparatus includes: a setting unit that makes authentication print settings such that when authentication information is inputted after image data is received, printing is executed based on the image data; and a transfer unit that, when the image data is received with the authentication print settings, in response to input of the authentication information, transfers the image data to a different apparatus, and when the image data is received without the authentication print settings, transfers the image data to the different apparatus regardless of input of the authentication information.

Abstract: A transmission device includes a controller that, in a case of transmitting a log of a transmission job to a server, controls forwarding such that each log remaining in the server is only a confirmed result for each transmission job.

Abstract: An image processing apparatus includes: a setting unit that makes authentication print settings such that when authentication information is inputted after image data is received, printing is executed based on the image data; and a transfer unit that, when the image data is received with the authentication print settings, in response to input of the authentication information, transfers the image data to a different apparatus, and when the image data is received without the authentication print settings, transfers the image data to the different apparatus regardless of input of the authentication information.

Abstract: A memory control device includes a memory control part that controls memory through an interface part in accordance with a predetermined communication regulation, an illegal access detection part that detects an illegal access to the memory according to an access state from the memory control part to the memory and a signal state of the interface part, and a signal control part that switches the signal state of the interface part from a write-allowed state, in which the interface part is able to be written, to a write-inhibited state, in which the interface part is protected from being rewritten, when the illegal access is detected by the illegal access detection part.

Abstract: A memory control device includes a memory control part that controls memory through an interface part in accordance with a predetermined communication regulation, an illegal access detection part that detects an illegal access to the memory according to an access state from the memory control part to the memory and a signal state of the interface part, and a signal control part that switches the signal state of the interface part from a write-allowed state, in which the interface part is able to be written, to a write-inhibited state, in which the interface part is protected from being rewritten, when the illegal access is detected by the illegal access detection part.

Abstract: An image processing apparatus includes an image reading unit for reading image data of an original; a communication unit for communicating through a communication network; an image data transmission unit for transmitting the image data to a server specified with an input operation of an operator through the communication unit; and an electric mail transmission unit for transmitting an electric mail to a destination specified with an input operation of the operator through the communication unit. The electric mail transmission unit is configured to transmit the electric mail including storage information of the image data in the server specified with the input operation of the operator and reading permission information of the image data to the destination specified with the input operation of the operator when the image data transmission unit transmits the image data to the server.

Abstract: An image data transfer circuit and an image data transfer method capable of exception processing without affecting image data of normal frames when an error is detected in image data. Image data applied to an input processing section is filtered by a filter, stored in an FIFO buffer, and sequentially read from an output section for transfer to the outside. In this event, two frame counters count numbers of frames which are being processed in input processing and output processing, respectively. When an error is detected in the input processing section, a stop controller does not output a stop request signal if the two count values do not match, and outputs the stop request signal at the time the two count values match. In this way, operations on error data are stopped after all image data of normal frames stored in the FIFO buffer has been transferred to the outside.

Abstract: A motion detection circuit calculates and updates a first Sum of Absolute Differences (SAD) between a reference macroblock stored in a reference macroblock buffer and a coding macroblock stored in a first coding macroblock buffer and calculates and updates a second SAD between a reference macroblock stored in the reference macroblock buffer and a coding macroblock stored in the second coding macroblock buffer. The motion detection circuit detects a reference macroblock, corresponding to the smallest of the updated first and second SAD values of each coding macroblock, as a predictive macroblock corresponding to the coding macroblock.

Abstract: In a circuit designing method for arithmetic elements to be employed in digital signal processing, a program is produced so that a directive is added to a target arithmetic operation which provides an overflow determination about desired digital signal processing. On the basis of this program, behavioral synthesis is performed. By adding an overflow detector to the target arithmetic operation, an RTL-description circuit is produced. The operation verification of the RTL-description circuit is performed to obtain the detection results of the overflow detector. When the RTL-description circuit is again produced on the basis of the operation verification results, the output bit length of the target arithmetic operation is optimized on the basis of the overflow detection results so that overflow is suppressed, whereby an optimized RTL-description circuit can be produced.

Abstract: An image data transfer circuit and an image data transfer method capable of exception processing without affecting image data of normal frames when an error is detected in image data. Image data applied to an input processing section is filtered by a filter, stored in an FIFO buffer, and sequentially read from an output section for transfer to the outside. In this event, two frame counters count numbers of frames which are being processed in input processing and output processing, respectively. When an error is detected in the input processing section, a stop controller does not output a stop request signal if the two count values do not match, and outputs the stop request signal at the time the two count values match. In this way, operations on error data are stopped after all image data of normal frames stored in the FIFO buffer has been transferred to the outside.

Abstract: A control method of the present invention comprises: a step for predetermining a priority level for accessing a slave via a bus with respect to a plurality of bus masters, as a basic priority; a step for determining a reference access frequency with respect to the plurality of bus masters, based on a required transfer rate; a step for counting an actual valid access frequency for each of the plurality of bus masters; a step for measuring a predetermined reference time; a step for determining an actual access priority of the plurality of bus masters based on the reference access frequency of the plurality of bus masters, the valid access frequency within the reference time, and the basic priority; and a step for granting access permission with respect to the plurality of bus masters, according to the actual access priority.

Abstract: Operation of a system including master and slave devices is verified through the use of system verification circuitry including a test master circuit that outputs test patterns on the system bus to emulate the operation of all master devices in the system, a built-in self-test and memory circuit that stores the test patterns and expected responses and compares the expected responses with the responses produced by the test patterns, and an interface circuit through which a host system downloads the test patterns and expected response values into the built-in self-test and memory circuit. Use of the test master circuit enables system and bus protocol features to be exercised fully without constraints arising from the limited capabilities of any one master device. The verification circuitry can be usefully incorporated together with the master and slave devices into a prototype system on a chip.

Abstract: A computation circuit which can obtain n+m-digit accumulation results by using an n-digit computation unit. This computation circuit comprises a computation unit which performs additions of n-digit data; an m-digit up/down counter; and a control circuit which uses the up/down counter to generate the upper m digits of the computation result. In a preferred embodiment, the control circuit increments by one the up/down counter when carry-over occurs in the computation unit, and when the input data of the computation unit is negative, decrements by one the up/down counter. In another preferred embodiment, the control circuit increments or decrements by one the up/down counter when positive or negative overflow occurs in the computation unit, and decrements by one the up/down counter when the final computation result of the computation unit is negative or is a positive number greater than 2n?1?1.

Abstract: A matrix type bus connection system has a plurality of master devices and a plurality of slave devices. Each slave device has an arbitration circuit. The arbitration circuit stores an address of a master device that made the access the last time, and continues holding a select signal to a selector when access ends. If a new connection request is received, the arbitration circuit compares the address of the master device that is now making the access request with the address of the master device that made the access the last time. If the connection request is from the same master device, a connection control is not performed. The previous connection status is maintained. Thus, the master device can be connected to the slave device without a delay.

Abstract: A computation circuit which can obtain n+m-digit accumulation results by using an n-digit computation unit. This computation circuit comprises a computation unit which performs additions of n-digit data; an m-digit up/down counter; and a control circuit which uses the up/down counter to generate the upper m digits of the computation result. In a preferred embodiment, the control circuit increments by one the up/down counter when carry-over occurs in the computation unit, and when the input data of the computation unit is negative, decrements by one the up/down counter. In another preferred embodiment, the control circuit increments or decrements by one the up/down counter when positive or negative overflow occurs in the computation unit, and decrements by one the up/down counter when the final computation result of the computation unit is negative or is a positive number greater than 2n−1−1.