Patents by Inventor Keitarou Niiyama

Keitarou Niiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scan test circuit, and method and program for designing same
    Patent number: 8402329
    Abstract: Flip-flops 201 to 206 constitute a scan path shift register. During shift mode operation, a clock signal CLK is supplied to clock terminals of the flip-flops 201, 203, and 205, a signal obtained by having an inverted clock control circuit 303 reverse the phase of the clock signal CLK is supplied to clock terminals of the flip-flops 202 and 206, and a normal/inverted clock control circuit 404 supplies a signal having the same phase as the clock signal CLK to a clock terminal of the flip-flop 204 having no sufficient setup time.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 19, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Keitarou Niiyama, Noriyuki Sakano, Yuuki Takahashi
  • SCAN TEST CIRCUIT, AND METHOD AND PROGRAM FOR DESIGNING SAME
    Publication number: 20100318862
    Abstract: Flip-flops 201 to 206 constitute a scan path shift register. During shift mode operation, a clock signal CLK is supplied to clock terminals of the flip-flops 201, 203, and 205, a signal obtained by having an inverted clock control circuit 303 reverse the phase of the clock signal CLK is supplied to clock terminals of the flip-flops 202 and 206, and a normal/inverted clock control circuit 404 supplies a signal having the same phase as the clock signal CLK to a clock terminal of the flip-flop 204 having no sufficient setup time.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 16, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: KEITAROU NIIYAMA, NORIYUKI SAKANO, YUUKI TAKAHASHI