Patents by Inventor Keith A. Benjamin

Keith A. Benjamin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12019912
    Abstract: An example embodiment includes an n-bit parallel pseudo-random binary sequence (PRBS) generator coupled to channelization circuitry to control the channelization circuitry to select from among a single channel n-bit output pattern from the PRBS generator and a number of multiple channel output patterns from the PRBS generator. The number of multiple channel output patterns can correspond to respective sub-patterns of the single channel n-bit output pattern.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: June 25, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Keith A. Benjamin
  • Patent number: 11921647
    Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: March 5, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Keith A Benjamin, Thomas Dougherty
  • Publication number: 20240012616
    Abstract: Methods, systems, and devices for a programmable finite field generator for memory are described. In some cases, a system (e.g., a memory system, a host system) may store coefficient values indicating Galois Field multipliers in an array of configuration registers associated with a finite field generator. To update a set of values stored in a set of registers associated with the finite field generator, the system may perform a set of Galois Field multiplication operations according to Galois Field multipliers indicated by the coefficient values stored in the array of configuration registers. The system may perform at least one Galois Field summation operation on one or more of the multiplied values to generate an updated value. Then, the system may store the updated value in a first register from the set of registers, and shift the set of values along the remaining set of registers.
    Type: Application
    Filed: July 11, 2022
    Publication date: January 11, 2024
    Inventor: Keith A. Benjamin
  • Patent number: 11868280
    Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Keith A Benjamin, Thomas Dougherty
  • Publication number: 20230145999
    Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
    Type: Application
    Filed: January 3, 2023
    Publication date: May 11, 2023
    Inventors: Keith A. Benjamin, Thomas Dougherty
  • Patent number: 11544203
    Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Keith A. Benjamin, Thomas Dougherty
  • Patent number: 11514995
    Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nathan A. Eckel, Keith A. Benjamin
  • Publication number: 20220365714
    Abstract: An example embodiment includes an n-bit parallel pseudo-random binary sequence (PRBS) generator coupled to channelization circuitry to control the channelization circuitry to select from among a single channel n-bit output pattern from the PRBS generator and a number of multiple channel output patterns from the PRBS generator. The number of multiple channel output patterns can correspond to respective sub-patterns of the single channel n-bit output pattern.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 17, 2022
    Inventor: Keith A. Benjamin
  • Patent number: 11353942
    Abstract: A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Keith A. Benjamin, Thomas Dougherty
  • Publication number: 20210210155
    Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.
    Type: Application
    Filed: March 24, 2021
    Publication date: July 8, 2021
    Inventors: Nathan A. Eckel, Keith A. Benjamin
  • Publication number: 20210200693
    Abstract: A system can include a plurality of sequencers each configured to provide a number of sequenced output signals responsive to assertion of a respective sequencer enable signal provided thereto. The system can include chaining circuitry coupled to the plurality of sequencers. The chaining circuitry can comprise logic to: responsive to assertion of a primary enable signal received thereby, assert respective sequencer enable signals provided to the plurality of sequencers in accordance with a first sequence; and responsive to deassertion of the primary enable signal, assert the respective sequencer enable signals provided to the plurality of sequencers in accordance with a second sequence.
    Type: Application
    Filed: March 12, 2020
    Publication date: July 1, 2021
    Inventors: Keith A. Benjamin, Thomas Dougherty
  • Publication number: 20210200292
    Abstract: A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.
    Type: Application
    Filed: December 18, 2020
    Publication date: July 1, 2021
    Inventors: Keith A. Benjamin, Thomas Dougherty
  • Publication number: 20210181978
    Abstract: A method includes receiving, by a memory sub-system and responsive to initiation of an operation, a bit string containing information corresponding to initiation of the operation. The operation can be initiated by circuitry external to the memory sub-system and the bit string can be generated by circuitry external to the memory sub-system. The method can further include storing, responsive to receipt of the bit string, the bit string in a first portion of a plurality of storage locations resident on the memory sub-system.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 17, 2021
    Inventors: Gary R. Van Sickle, Jacob Sloat, Keith A. Benjamin
  • Patent number: 10984881
    Abstract: A method includes requesting, by a component of a memory sub-system controller, control of a data path associated with a memory device coupleable to the controller. The method can include generating, by the component, data corresponding to an operation to test the memory device and causing, by the component, the data to be injected to the data path such that the data is written to the memory device. The method can further include reading, by the component, the data written to the memory device and determining, by the component, whether the data read by the component from the memory device matches the data written to the memory device.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 20, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Nathan A. Eckel, Keith A. Benjamin
  • Patent number: 10877541
    Abstract: A system can comprise a memory device and sequencing circuitry configured to provide enable signals to a number of voltage regulators in association with providing sequenced power signals to the memory device. The system can include voltage threshold detection circuitry configured to: detect primary supply voltage events; and responsive to detecting a primary supply voltage event, deassert a timer enable signal provided to timing circuitry. The timing circuitry is configured to, responsive to the deassertion of the timer enable signal: deassert a primary enable signal provided to the sequencing circuitry; and maintain the primary enable signal in a deasserted state for a particular amount of time prior to reasserting the primary enable signal.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Keith A. Benjamin, Thomas Dougherty