Abstract: A tray (10') for handling a semiconductor device encapsulated in a package body and having multiple electrical I/Os projecting from the package body has cell-to-cell interlocking capability as well as invertibility. An interlocking nest feature (16) is formed on the underside of the tray and interfaces with the cells (12') on the topside of the tray (10') when the trays are stacked. The interlocking nest feature has an external chamfer (20) which mates with a lead-in chamfer (18) of the tray cell to align the interlocking feature (16) and the cell (12'). The interlocking nest feature (16) has an internal device retaining chamfer (22) and a device capture surface (26) to guide and retain the semiconductor device when stacking trays, inverting trays or processing semiconductor devices with the trays inverted. In-tray inspection and electrical test are also possible using a test contactor having a functional equivalent of the interlocking nest feature.