Patents by Inventor Keith A. Bowman

Keith A. Bowman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190321295
    Abstract: Encapsulated nucleic acid nanoparticles of uniformly small particle size are produced by intersecting one or more nucleic acid streams with one or more lipid streams. The encapsulated nucleic acid nanoparticles include a nucleic acid encapsulated within a lipid nanoparticle host. Uniformly small particle sizes are obtained by intersecting an aqueous nucleic acid stream and a stream of lipids in organic solvent at high linear velocities and with total organic solvent concentrations less than 33%.
    Type: Application
    Filed: May 30, 2019
    Publication date: October 24, 2019
    Inventors: Keith A. Bowman, Noah Gardner, Travis Jeannotte, Chandra Vargeese
  • Patent number: 10342761
    Abstract: Encapsulated nucleic acid nanoparticles of uniformly small particle size are produced by intersecting one or more nucleic acid streams with one or more lipid streams. The encapsulated nucleic acid nanoparticles include a nucleic acid encapsulated within a lipid nanoparticle host. Uniformly small particle sizes are obtained by intersecting an aqueous nucleic acid stream and a stream of lipids in organic solvent at high linear velocities and with total organic solvent concentrations less than 33%.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: July 9, 2019
    Assignee: Novartis AG
    Inventors: Keith A. Bowman, Noah Gardner, Travis Jeannotte, Chandra Vargeese
  • Patent number: 10024916
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: July 17, 2018
    Assignee: INTEL CORPORATION
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
  • Patent number: 9772903
    Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 26, 2017
    Assignee: INTEL CORPORATION
    Inventors: Jaydeep P. Kulkarni, Keith A. Bowman, James W. Tschanz, Vivek K. De
  • Publication number: 20170196809
    Abstract: Encapsulated nucleic acid nanoparticles of uniformly small particle size are produced by intersecting one or more nucleic acid streams with one or more lipid streams. The encapsulated nucleic acid nanoparticles include a nucleic acid encapsulated within a lipid nanoparticle host. Uniformly small particle sizes are obtained by intersecting an aqueous nucleic acid stream and a stream of lipids in organic solvent at high linear velocities and with total organic solvent concentrations less than 33%.
    Type: Application
    Filed: July 10, 2015
    Publication date: July 13, 2017
    Inventors: Keith A. BOWMAN, Noah GARDNER, Travis JEANNOTTE, Chandra VARGEESE
  • Publication number: 20170139006
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Application
    Filed: February 1, 2017
    Publication date: May 18, 2017
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
  • Patent number: 9594625
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
  • Publication number: 20160210192
    Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: Jaydeep P. Kulkarni, Keith A. Bowman, James W. Tschanz, Vivek K. De
  • Patent number: 9329918
    Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: May 3, 2016
    Assignee: INTEL CORPORATION
    Inventors: Jaydeep P. Kulkarni, Keith A. Bowman, James W. Tschanz, Vivek K. De
  • Publication number: 20160034338
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Application
    Filed: October 8, 2015
    Publication date: February 4, 2016
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
  • Patent number: 9229054
    Abstract: An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single-transition DC-stressed path delay; and therefore enables the adjustment of the frequency of the dock signal to correspond to an amount or effect of the delay.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: January 5, 2016
    Assignee: Intel Corporation
    Inventors: Keith A. Bowman, Carlos Tokunaga, James W. Tschanz
  • Patent number: 9189014
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: November 17, 2015
    Assignee: Intel Corporation
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
  • Publication number: 20140122947
    Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
    Type: Application
    Filed: October 30, 2012
    Publication date: May 1, 2014
    Inventors: Keith A. Bowman, James W. Tschanz, Nam Sung Kim, Janice C. Lee, Christopher B. Wilkerson, Shih-Lien L. Lu, Tanay Karnik, Vivek K. De
  • Publication number: 20140032980
    Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.
    Type: Application
    Filed: December 28, 2011
    Publication date: January 30, 2014
    Inventors: Jaydeep P. Kulkarni, Keith A. Bowman, James W. Tschanz, Vivek K. De
  • Publication number: 20130285685
    Abstract: An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single transition DC-stressed path delay, and therefore enables the adjustment of the frequency of the clock signal to correspond to an amount or effect of the delay.
    Type: Application
    Filed: September 28, 2011
    Publication date: October 31, 2013
    Inventors: Keith A. Bowman, Carlos Tokunaga, James W. Tschanz
  • Publication number: 20110224447
    Abstract: The instant invention provides for novel lipid nanoparticles and novel lipid nanoparticle components (specifically cationic lipids) that are useful for the delivery of nucleic acids, specifically siRNA, for therapeutic purposes.
    Type: Application
    Filed: August 11, 2009
    Publication date: September 15, 2011
    Inventors: Keith A. Bowman, James P. Guare, JR., George D. Hartman, Rubina G. Parmar, Chandra Vargeese, Weimin Wang, Ye Zhang
  • Patent number: 7653850
    Abstract: Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: January 26, 2010
    Assignee: Intel Corporation
    Inventors: James W. Tschanz, Keith A. Bowman, Nam Sung Kim, Chris Wilkerson, Shih-Lien L. Lu, Tanay Karnik
  • Publication number: 20080307277
    Abstract: Some embodiments provide sampling of a data signal output from a path stage using a latch, sampling of the data signal output from the path stage using an edge-triggered flip-flop, comparing a first value output by the latch with a second value output by the edge-triggered flip-flop, and generating an error signal if the first value is different from the second value.
    Type: Application
    Filed: June 5, 2007
    Publication date: December 11, 2008
    Inventors: James W. Tschanz, Keith A. Bowman, Nam Sung Kim, Chris Wilkerson, Shih-Lien L. Lu, Tanay Karnik