Abstract: A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format.

Abstract: A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format.

Abstract: A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.

Abstract: An asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device.

Abstract: A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) one or more control signals. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of one or more of the enable signals generally reduces current consumption in the memory array.

Abstract: An asynchronous memory device includes parallel test circuitry configured to interface with a single-ended output data path of the memory device and, in some cases, to provide a measure of a slowest cell access time for the memory device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the memory device and to provide first output signals indicative of logic states of the plurality of cells; and second circuitry configured to receive the first output signals and to produce a second output signal indicative of the logic states of the first output signals therefrom. For example, the first circuitry and the second circuitry may be configured as a wired NAND and wired NOR combination. In some cases, one or more of the cells may be included within a redundant row or column of the memory device.

Abstract: A method for providing at least 2 Meg of SRAM cells having a maximum average operating current of approximately 9.43 mA comprising the steps of (A) providing an address path configured to consume a maximum average operating current of approximately 2.38 mA, (B) providing one or more sense amplifiers configured to consume a maximum average operating current of approximately 0.91 mA, (C) providing one or more bitlines configured to consume a maximum average operating current of approximately 0.94 mA and (D) providing a Q path configured to consume a maximum average operating current of approximately 0.61 mA.

Abstract: A circuit comprising a plurality of groups of memory cells and a control circuit. The plurality of groups of memory cells may each (i) have a first and a second bitline and (ii) configured to read and write data to one or more of the plurality of groups of memory cells. The control circuit may be configured to select an active group of the plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

Abstract: An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the first output signals and to produce second output signals indicative of logic states of the first output signals therefrom. The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry.

Abstract: A circuit for addressing leakage. The circuit may have a variable supply stage having an active load in parallel with a switch transistor where the active load and the switch transistor are coupled to a decoupling capacitor. The circuit may also have a leakage detect stage having a leak device coupled to a critical node. An embodiment of the circuit may have a supply node; an input node; an output node; a buffer stage where the buffer stage supply node is coupled to a variable supply stage output, the buffer stage input is coupled to the input node and the buffer stage output is coupled to the output node; a leakage detect stage where the leakage detect stage supply node is coupled to the supply node and the leakage detect stage input is coupled to the input node; and a variable supply stage where the variable supply stage supply node is coupled to the supply node and the variable supply stage input is coupled to the leakage detect stage output.

Abstract: A circuit comprising a memory array and a logic circuit. The memory array may be configured to read or write data in response to (i) one or more enable signals and (ii) a global signal. The logic circuit may be configured to generate the enable signals in response to one or more address signals. De-assertion of the enable signals generally reduces current consumption in the memory array.

Abstract: A circuit comprising a first and second bitline, a plurality of groups of memory cells and a control circuit. The first and second bitlines may each be configured to read and write to one or more of the plurality of groups of memory cells. Each of the plurality of bitline pairs may be interdigitated. The control circuit may be configured to select an active group of said plurality of groups in response to one or more control signals. The control circuit may be implemented within the groups of memory cells.

Abstract: An asynchronous memory device includes parallel test circuitry configured to provide a measure of a slowest bit access time for the device. The parallel test circuitry may include first circuitry configured to receive logic signals from a plurality of cells of the device and to provide first output signals indicative of logic states of the plurality of cells. The parallel test circuitry may also include second circuitry configured to receive the fist output signals and to produce second output signals indicative of logic states of the first output signals therefor The parallel test circuitry may be the same circuitry used in the read path of the memory device, and may be configured such that the second output signals are produced at the slowest bit access time. The plurality of cells tested may include a redundant cell of the device. Such redundancy is transparent to the test circuitry.

Abstract: A method and apparatus for reducing noise in a memory bit-line pull-up circuit. The memory bit-line pull-up circuit includes a first reference line, a second reference line, a first capacitor, a gating device, and a pull-down circuit. The circuit may further include a load transistor coupled between the first reference line and a first voltage conduit, which generally maintains the voltage on the first reference line at Vcc-Vt, and a second capacitor and the load transistor providing a pull-up path for the voltage on the first reference line when Vcc increases and the first capacitor. The pull-down circuit provides a pull-down path for the voltage on the first reference line when Vcc decreases. The first capacitor provides a pull-up path for the voltage on the second reference line. A first gating device couples a bit-line to the first reference line. The circuit further including a second gating device to couple a bit-line bar to the first reference line.