Patents by Inventor Keith A. Lowery

Keith A. Lowery has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140047272
    Abstract: The present disclosure relates to a method and system for configuring a computing system, such as a cloud computing system. A method includes selecting, based on a user selection received via a user interface, a workload for execution on a cluster of nodes of the computing system. The workload is selected from a plurality of available workloads including an actual workload and a synthetic test workload. The method further includes configuring the cluster of nodes of the computing system to execute the selected workload such that processing of the selected workload is distributed across the cluster of nodes. The synthetic test workload may be generated by a code synthesizer based on a set of user-defined workload parameters provided via a user interface that identify execution characteristics of the synthetic test workload.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Mauricio Breternitz, Keith A. Lowery, Patryk Kaminski, Anton Chernoff
  • Patent number: 8572326
    Abstract: A method and system for dynamic distributed data caching is presented. The method includes establishing a cache community of members for data storage. A request for data at a particular member of the cache community is generated. A cache location in the cache community where the data would be located is determined. A determination is made as to whether the data is stored at the cache location. The data is requested from a source of the data in response to the data not being cached at the cache location. A determination is made as to whether the source is currently unavailable to provide the data. The data is continuously requested from the source while waiting for the source to become available. The particular member is allowed to request other data while waiting for data to become available from the source.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: October 29, 2013
    Assignee: Parallel Networks, LLC
    Inventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
  • Publication number: 20130263144
    Abstract: Embodiments described herein include a system, a computer-readable medium and a computer-implemented method for processing a system call (SYSCALL) request. The SYSCALL request from an invisible processing device is stored in a queueing mechanism that is accessible to a visible processing device, where the visible processing device is visible to an operating system and the invisible processing device is invisible to the operating system. The SYSCALL request is processed using the visible processing device, and the invisible processing device is notified using a notification mechanism that the SYSCALL request was processed.
    Type: Application
    Filed: March 29, 2013
    Publication date: October 3, 2013
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Benjamin Thomas Sander, Michael Clair Houston, Keith Lowery, Newton Cheung
  • Patent number: 8504663
    Abstract: A cache module (26) at a client computer (12) controls a cache portion (28) on a storage device (24). The cache module communicates with other cache modules at other clients to form a cache community (15). The cache modules store World Wide Web or other content in the cache portions for retrieval in response to requests (32) for content from browsers (30) in the cache community. When the requested content is not available in the cache community, the requested content may be retrieved from an origin server (19) using the Internet.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: August 6, 2013
    Assignee: Parallel Networks, LLC
    Inventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
  • Publication number: 20130031060
    Abstract: When requested content is available at a data center, the data center returns the requested content to the data center. When the requested content is locally unavailable at the data center, the requested content is retrieved from an origin server. The retrieval of the content from the origin server may be delayed based on the processing load at the origin server. When retrieval of the content is delayed, the request is prioritized and placed in a queue for handling by the origin server based on the priority of the request. Also, when retrieval of the content is delayed, a status page may be communicated to the browser to inform a user of the delay and provide alternate content and status information related to the request determined as a function of the request or the current state of the origin server.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 31, 2013
    Applicant: Parallel Networks, LLC
    Inventors: Keith A. Lowery, David K. Davidson, Avinash C. Saxena
  • Publication number: 20130007188
    Abstract: A cache module (26) at a client computer (12) controls a cache portion (28) on a storage device (24). The cache module communicates with other cache modules at other clients to form a cache community (15). The cache modules store World Wide Web or other content in the cache portions for retrieval in response to requests (32) for content from browsers (30) in the cache community. When the requested content is not available in the cache community, the requested content may be retrieved from an origin server (19) using the Internet.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 3, 2013
    Applicant: Parallel Networks, LLC
    Inventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
  • Publication number: 20120331278
    Abstract: A system and method for automatically optimizing parallel execution of multiple work units in a processor by reducing a number of branch instructions. A computing system includes a first processor core with a general-purpose micro-architecture and a second processor core with a same instruction multiple data (SIMD) micro-architecture. A compiler detects and evaluates branches within function calls with one or more records of data used to determine one or more outcomes. Multiple compute sub-kernels are generated, each comprising code from the function corresponding to a unique outcome of the branch. Multiple work units are produced by assigning one or more records of data corresponding to a given outcome of the branch to one of the multiple compute sub-kernels associated with the given outcome. The branch is removed. An operating system scheduler schedules each of the one or more compute sub-kernels to the first processor core or to the second processor core.
    Type: Application
    Filed: June 23, 2011
    Publication date: December 27, 2012
    Inventors: Mauricio Breternitz, Patryk Kaminski, Keith Lowery
  • Publication number: 20120297163
    Abstract: A system and method for automatically migrating the execution of work units between multiple heterogeneous cores. A computing system includes a first processor core with a single instruction multiple data micro-architecture and a second processor core with a general-purpose micro-architecture. A compiler predicts execution of a function call in a program migrates at a given location to a different processor core. The compiler creates a data structure to support moving live values associated with the execution of the function call at the given location. An operating system (OS) scheduler schedules at least code before the given location in program order to the first processor core. In response to receiving an indication that a condition for migration is satisfied, the OS scheduler moves the live values to a location indicated by the data structure for access by the second processor core and schedules code after the given location to the second processor core.
    Type: Application
    Filed: May 16, 2011
    Publication date: November 22, 2012
    Inventors: Mauricio Breternitz, Patryk Kaminski, Keith Lowery, Anton Chernoff, Dz-Ching Ju
  • Publication number: 20120291040
    Abstract: A system and method for efficient automatic scheduling of the execution of work units between multiple heterogeneous processor cores. A processing node includes a first processor core with a general-purpose micro-architecture and a second processor core with a single instruction multiple data micro-architecture. A computer program comprises one or more compute kernels, or function calls. A compiler computes pre-runtime information of the given function call. A runtime scheduler produces one or more work units by matching each of the one or more kernels with an associated record of data. The scheduler assigns work units either to the first or to the second processor core based at least in part on the computed pre-runtime information. In addition, the scheduler is able to change an original assignment for a waiting work unit based on dynamic runtime behavior of other work units corresponding to a same kernel as the waiting work unit.
    Type: Application
    Filed: May 11, 2011
    Publication date: November 15, 2012
    Inventors: Mauricio Breternitz, Patryk Kaminski, Keith Lowery, Anton Chernoff
  • Patent number: 8296451
    Abstract: A data center determines whether requested content is available at the data center. The content is available when the content is both present at the data center and current. When the requested content is available at the data center, the data center returns the requested content to the browser. When the requested content is locally unavailable at the data center, the requested content is retrieved from an origin server. When retrieval of the content is delayed, the request is prioritized and placed in a queue for handling by the origin server based on the priority of the request. A status page may be communicated to the browser to inform a user of the delay and provide alternate content and status information related to the request determined as a function of the request or the current state of the origin server.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: October 23, 2012
    Assignee: Parallel Networks, LLC
    Inventors: Keith A. Lowery, David K. Davidson, Avinash C. Saxena
  • Publication number: 20120254341
    Abstract: A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.
    Type: Application
    Filed: June 18, 2012
    Publication date: October 4, 2012
    Applicant: Parallel Networks, LLC
    Inventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
  • Patent number: 8271628
    Abstract: A cache module (26) at a client computer (12) controls a cache portion (28) on a storage device (24). The cache module communicates with other cache modules at other clients to form a cache community (15). The cache modules store World Wide Web or other content in the cache portions for retrieval in response to requests (32) for content from browsers (30) in the cache community. When the requested content is not available in the cache community, the requested content may be retrieved from an origin server (19) using the Internet.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: September 18, 2012
    Assignee: Parallel Networks, LLC
    Inventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
  • Patent number: 8245008
    Abstract: A system and method for allocating memory to multi-threaded programs on a Non-Uniform Memory Access (NUMA) computer system using a NUMA-aware memory heap manager is disclosed. In embodiments, a NUMA-aware memory heap manager may attempt to maximize the locality of memory allocations in a NUMA system by allocating memory blocks that are near, or on the same node, as the thread that requested the memory allocation. A heap manager may keep track of each memory block's location and satisfy allocation requests by determining an allocation node dependent, at least in part, on its locality to that of the requesting thread. When possible, a heap manger may attempt to allocate memory on the same node as the requesting thread. The heap manager may be non-application-specific, may employ multiple levels of free block caching, and/or may employ various listings that associate given memory blocks with each NUMA node.
    Type: Grant
    Filed: February 18, 2009
    Date of Patent: August 14, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Patryk Kaminski, Keith Lowery
  • Publication number: 20120194526
    Abstract: Systems, methods, and articles of manufacture for optimizing task scheduling on an accelerated processing device (APD) device are provided. In an embodiment, a method comprises: enqueuing, using the APD, one or more tasks in a memory storage; and dequeuing, using the APD, the one or more tasks from the memory storage using a hardware-based command processor, wherein the command processor forwards the one or more tasks to a shader core.
    Type: Application
    Filed: November 30, 2011
    Publication date: August 2, 2012
    Inventors: Benjamin Thomas SANDER, Michael Houston, Newton Cheung, Keith Lowery
  • Publication number: 20120192201
    Abstract: A method, system and article of manufacture for balancing a workload on heterogeneous processing devices.
    Type: Application
    Filed: November 2, 2011
    Publication date: July 26, 2012
    Inventors: Benjamin Thomas SANDER, Michael Houston, Newton Cheung, Keith Lowery
  • Publication number: 20120179851
    Abstract: A system, method and article of manufacture for an accelerated processing device (APD) to request a central processing unit (CPU) to process a task, comprising enqueuing a plurality of tasks on a queue using the APD, generating a user-level interrupt and transmitting to the CPU the plurality of tasks in the queue using an interrupt handler associated with a CPU thread.
    Type: Application
    Filed: November 9, 2011
    Publication date: July 12, 2012
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Benjamin Thomas SANDER, Michael Houston, Newton Cheung, Keith Lowery
  • Publication number: 20120180056
    Abstract: Methods, systems and computer-readable mediums for task scheduling on an accelerated processing device (APD) are provided. In an embodiment, a method comprises: enqueuing one or more tasks in a memory storage module based on the APD; using a software-based enqueuing module; and dequeuing the one or more tasks from the memory storage module using a hardware-based command processor, wherein the command processor forwards the one or more tasks to the shader cote.
    Type: Application
    Filed: November 9, 2011
    Publication date: July 12, 2012
    Inventors: Benjamin Thomas SANDER, Michael Houston, Newton Cheung, Keith Lowery
  • Publication number: 20120179773
    Abstract: A cache module (26) at a client computer (12) controls a cache portion (28) on a storage device (24). The cache module communicates with other cache modules at other clients to form a cache community (15). The cache modules store World Wide Web or other content in the cache portions for retrieval in response to requests (32) for content from browsers (30) in the cache community. When the requested content is not available in the cache community, the requested content may be retrieved from an origin server (19) using the Internet.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 12, 2012
    Applicant: Parallel Networks, LLC
    Inventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters
  • Publication number: 20120180072
    Abstract: Provided herein is a method for optimizing communication for system calls. The method includes storing a system call for each work item in a wavefront and transmitting said stored system calls to a processor for execution. The method also includes receiving a result to each work item in the wavefront responsive to said transmitting.
    Type: Application
    Filed: November 30, 2011
    Publication date: July 12, 2012
    Inventors: Benjamin Thomas SANDER, Michael Houston, Newton Cheung, Keith Lowery
  • Patent number: 8205044
    Abstract: A method and system for dynamic distributed data caching is presented. The system includes one or more peer members and a master member. The master member and the one or more peer members form cache community for data storage. The master member is operable to select one of the one or more peer members to become a new master member. The master member is operable to update a peer list for the cache community by removing itself from the peer list. The master member is operable to send a nominate master message and an updated peer list to a peer member selected by the master member to become the new master member.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: June 19, 2012
    Assignee: Parallel Networks, LLC
    Inventors: Keith A. Lowery, Bryan S. Chin, David A. Consolver, Gregg A. DeMasters