Abstract: An improved circuit board structure and method of forming the same are provided. The circuit board includes an insulating core and has plated through holes connecting the circuitry on both sides and intermediate layers of the core. A permanent dielectric material is applied on at least one surface of the board covering the circuitry and plated through holes. Vias are formed through the dielectric material and signal lines are formed on the top of the dielectric material connected to the circuitry onto the board through the vias. Additional layers of dielectric material with additional wiring and vias can also be formed for multi-level wiring.

Abstract: A connector assembly for connecting several coaxial cables to a circuit board such that the center conductors of each cable are inserted within a conductive hole which forms part of the board structure. The assembly includes a common housing which may be electrically conductive or insulative and a spring contact member which serves as part of the grounding means to effectively ground the shield members of the coaxial cables to the board's ground. The spring contacts may be in the form of resilient springs which extend from the assembly or of compressible members coupled to a conductive layer which in turn is connected to the shield members. An apparatus for positioning more than one such assembly on a common board structure is also shown and described, as is an assembly designed for positioning the cables therein in a substantially compact orientation.

Abstract: An improved circuit board structure and method of forming the same are provided. The circuit board includes an insulating core and has plated through holes connecting the circuitry on both sides and intermediate layers of the core. A permanent dielectric material is applied on at least one surface of the board covering the circuitry and plated through holes. Vias are formed through the dielectric material and signal lines are formed on the top of the dielectric material connected to the circuitry onto the board through the vias. Additional layers of dielectric material with additional wiring and vias can also be formed for multi-level wiring.

Abstract: The disclosure describes a new and improved Tape Automated Bonding package which admits of certain advantages that are not available with the packages as used in the past, and it overcomes some limitations with the previous packages which permits a significant step forward in realizing these advantages.Briefly, the disclosure describes a division of the dielectric support used to package integrated circuit chips in order to separate the power conductors and the signal conductors into different parts of the support. The conductors formed on at least one of these parts, preferably the part used to connect input/output signals to and from a chip, are arranged in radially extending rows to achieve more than twice the number of such connections.

Abstract: A process for providing circuit lines on a substrate having a non-planar surface is provided. The process includes applying a layer of photoresist material to the substrate, selectively screen printing on non-planar areas of the substrate a screen-printable coating, photoprocessing the layer of photoresist material, and providing electrical conductive pattern on the substrate.

Abstract: A process is provided for making a multilayer integrated circuit substrate having improved via connection. A first layer M1 of chrome-copper-chrome is applied to a ceramic substrate and the circuits etched. A polyimide layer is then applied, cured, and developed and etched to provide via holes in the polyimide down to the M1 circuitry. The top chrome is now etched to expose the M1 copper in the via holes. A second layer M2 of copper-chrome is evaporated onto the polyimide at a high substrate temperature to provide a copper interface at the base of the vias having no visable grain boundaries and a low resistance. M2 circuitization is then carried out.

Abstract: In a field-accessed magnetic domain device package assembly, the magnetic domain device carrier or support, the circuit line or conductor carrier, and the magnetic bias field source are integrally and coactively provided by a common substrate member. The member is a planar permanent magnetic insulator ceramic and carries a bonded conductor or wiring pattern. The input/output (I/O) terminals of the domain device, also referred to in the art as a chip, are selectively bonded to the conductors of the pattern thereby providing mechanical support of the chip directly to the substrate in a superimposed relationship, input/output electrical connection to the chip, and mounting of the chip in close proximity to the bias field source, the flux of which passes through the superimposed mounted chips to a high permeability member at least part of which is disposed on the opposite side of the chip.