Abstract: Method embodiments are provided herein for dynamically calibrating and adjusting a direct conversion receiver system. One embodiment includes applying one or more gain control signals to one or more gain elements of a receiver system, where the applying one or more gain control signals results in a gain change to the receiver system; in response to the gain change, determining whether the receiver system exhibits a DC (direct conversion) offset; and in response to a determination that the receiver system exhibits the DC offset, applying one or more DC offset correction control signals to one or more gain elements of the receiver system, where the one or more DC offset correction signals are configured to correct the DC offset.

Abstract: A DC offset correction method and apparatus. In a differential system, a DC offset correction loop includes a gain stage (104) having a differential input, a gain G and a differential output. A DAC circuit (130) provides a correction DC signal at the inputs to produce differential output signals Vo′ and {overscore (Vo)}′. A controller (120) corrects the DC offset by stepping the DAC circuit (130) to change the correction DC signal by an amount equal to approximately (Vo′−{overscore (Vo′)})/Gx, where GX is the gain G times the gain of the DAC expressed in volts per DAC step. A similar algorithm can be applied to single ended systems wherein a single ended VOFFSET is corrected by an amount equal to approximately VOFFSET/Gx.

Abstract: A receiver includes a main loop (222) having a main VCO (210) and a secondary loop (224) having a secondary VCO (216). The receiver momentarily phase locks an incoming RF signal (228), and then samples and stores a correction voltage (240) being applied to the main VCO (210). The main loop (222) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit (218) to the main VCO (210) for the duration of the incoming RF signal (228). This effectively calibrates the LO frequency (230) of the receiver to the incoming RF signal frequency (228).

Abstract: A DC offset correction method and apparatus. In a DC offset correction loop (100), a DC offset is corrected using a binary search routine or any other digital or analog DC offset correction technique. In this binary search routine, the sign of the offset (138) is used to control a direction in which a digital to analog converter (DAC) (166) is stepped until the least significant bit of the DAC is set. The process is enhanced by opening up the bandwidth of the baseband filters (130) to permit the binary search to be clocked (180) at a higher clock rate. After the correction is established, the filters (130) are reset to normal operating conditions.

Abstract: A DC offset correction method and apparatus. Several DC offset correction schemes including a digital binary search scheme (100), a digital slow averaging scheme (200) and an analog integration (50) scheme are provided. A controller (160) selects one or more of the correction schemes in accordance with the desired characteristics provided by each scheme.

Abstract: A DC offset correction loop (200) utilizes a sign bit generator (204), binary search stage (206), and a digital-to-analog converter (208) in its feedback path to correct for DC offsets at the input of a gain stage (202). When a correction value is obtained, it is applied and held (524) to compensate for the DC offset. When a programming event occurs (534), such as detecting an increase in DC offset beyond a threshold, detecting a significant temperature change, or passage of time, a new DC offset correction cycle is initiated.

Abstract: A receiver includes a main loop (222) having a main VCO (210) and a secondary loop (224) having a secondary VCO (216). The receiver momentarily phase locks an incoming RF signal (228), and then samples and stores a correction voltage (240) being applied to the main VCO (210). The main loop (222) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit (218) to the main VCO (210) for the duration of the incoming RF signal (228). This effectively calibrates the LO frequency (230) of the receiver to the incoming RF signal frequency (228).

Abstract: A DC offset correction loop (200) utilizes a sign bit generator (204), binary search stage (206), and a digital-to-analog converter (208) in its feedback path to correct for DC offsets at the input of a gain stage (202).