Patents by Inventor Keith Alan Bowman
Keith Alan Bowman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11880454Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.Type: GrantFiled: May 14, 2020Date of Patent: January 23, 2024Assignee: QUALCOMM IncorporatedInventors: Bharat Kumar Rangarajan, Dipti Ranjan Pal, Keith Alan Bowman, Srinivas Turaga, Ateesh Deepankar De, Shih-Hsin Jason Hu, Chandan Agarwalla
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Patent number: 11855645Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.Type: GrantFiled: September 25, 2021Date of Patent: December 26, 2023Assignee: QUALCOMM INCORPORATEDInventors: Keith Alan Bowman, Daniel Yingling, Dipti Ranjan Pal
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Publication number: 20230096760Abstract: Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.Type: ApplicationFiled: September 25, 2021Publication date: March 30, 2023Inventors: Keith Alan BOWMAN, Daniel YINGLING, Dipti Ranjan PAL
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Publication number: 20220365580Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.Type: ApplicationFiled: May 17, 2021Publication date: November 17, 2022Inventors: VIJAYAKUMAR ASHOK DIBBAD, Bharat Kumar RANGARAJAN, Dipti Ranjan PAL, Keith Alan BOWMAN, Matthew SEVERSON, Gordon LEE
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Patent number: 11493980Abstract: In controlling power in a portable computing device (“PCD”), a power supply input to a PCD subsystem may be modulated with a modulation signal when an over-current condition is detected. Detection of the modulation signal may indicate to a processing core of the subsystem to reduce its processing load. Compensation for the modulation signal in the power supply input may be applied so that the processing core is essentially unaffected by the modulation signal.Type: GrantFiled: May 17, 2021Date of Patent: November 8, 2022Assignee: QUALCOMM IncorporatedInventors: Vijayakumar Ashok Dibbad, Bharat Kumar Rangarajan, Dipti Ranjan Pal, Keith Alan Bowman, Matthew Severson, Gordon Lee
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Patent number: 11424736Abstract: Aspects of the present disclosure related to a method of phase extension using a delay circuit including delay devices coupled in series. The method includes receiving a clock signal, generating multiple delayed versions of the clock signal, wherein each of the delayed versions of the clock signal is delayed by a different number of the delay devices, and combining high phases or low phases of the delayed versions of the clock signal to obtain a combined clock signal.Type: GrantFiled: September 25, 2021Date of Patent: August 23, 2022Assignee: QUALCOMM INCORPORATEDInventors: Keith Alan Bowman, Daniel Yingling, Dipti Ranjan Pal
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Patent number: 11398812Abstract: A method of measuring a clock signal includes launching an edge of a timing signal on a first edge of the clock signal, outputting an edge of a capture signal on a second edge of the clock signal, receiving the edge of the timing signal and the edge of the capture signal at a time-to-digital converter (TDC), and measuring a time delay using the TDC, wherein the time delay is between a time the edge of the timing signal is received at the TDC and a time the edge of the capture signal is received at the TDC.Type: GrantFiled: September 25, 2021Date of Patent: July 26, 2022Assignee: QUALCOMM INCORPORATEDInventors: Keith Alan Bowman, Daniel Yingling, Dipti Ranjan Pal
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Patent number: 11270761Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.Type: GrantFiled: April 6, 2021Date of Patent: March 8, 2022Assignee: Qualcomm IncorporatedInventors: Hoan Huu Nguyen, Francois Ibrahim Atallah, Keith Alan Bowman, Daniel Yingling, Jihoon Jeong, Yu Pu
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Patent number: 11264976Abstract: Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.Type: GrantFiled: June 19, 2020Date of Patent: March 1, 2022Assignee: QUALCOMM INCORPORATEDInventors: Fadi Hamdan, Keith Alan Bowman, Nadeem Eleyan, Xiang Li
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Patent number: 11249530Abstract: In certain aspects, a system includes a voltage controller, wherein the voltage controller includes switches coupled between a voltage supply rail and an output of the voltage controller, each of the switches having a control input, and a control circuit coupled to the control inputs of the switches. The system also includes a timing circuit coupled to the control circuit, wherein the timing circuit includes a delay line, and flops, each of the flops having an input and an output, wherein the input of each of the flops is coupled to a respective node on the delay line, and the outputs of the flops are coupled to the control circuit.Type: GrantFiled: November 25, 2020Date of Patent: February 15, 2022Assignee: QUALCOMM INCORPORATEDInventors: Dipti Ranjan Pal, Harshat Pant, Abinash Roy, Shih-Hsin Jason Hu, Keith Alan Bowman
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Publication number: 20210399722Abstract: Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.Type: ApplicationFiled: June 19, 2020Publication date: December 23, 2021Inventors: Fadi HAMDAN, Keith Alan BOWMAN, Nadeem ELEYAN, Xiang LI
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Publication number: 20210357502Abstract: A method to prevent a malicious attack on CPU subsystem (CPUSS) hardware is described. The method includes auto-calibrating tunable delay elements of a dynamic variation monitor (DVM) using an auto-calibration value computed in response to each detected change of a clock frequency (Fclk)/supply voltage (Vdd) of the CPUSS hardware. The method also includes comparing the auto-calibration value with a threshold reference calibration value to determine whether the malicious attack is detected. The method further includes forcing a safe clock frequency (Fclk)/safe supply voltage (Vdd) to the CPUSS hardware when the malicious attack is detected.Type: ApplicationFiled: May 14, 2020Publication date: November 18, 2021Inventors: Bharat Kumar RANGARAJAN, Dipti Ranjan PAL, Keith Alan BOWMAN, Srinivas TURAGA, Ateesh Deepankar DE, Shih-Hsin Jason HU, Chandan AGARWALLA
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Publication number: 20210225435Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.Type: ApplicationFiled: April 6, 2021Publication date: July 22, 2021Inventors: Hoan Huu NGUYEN, Francois Ibrahim ATALLAH, Keith Alan BOWMAN, Daniel YINGLING, Jihoon JEONG, Yu PU
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Patent number: 11031075Abstract: A high bandwidth register file circuit that significantly reduces the shared local read bitline RC delay to enable ultra-high performance PRFs with high port counts. In one example, the register file circuit includes read stack nfets in a multiplexer circuit instead of the memory cell causing the local read bitline RC to be independent of the number of read and write ports of the memory cell.Type: GrantFiled: May 8, 2019Date of Patent: June 8, 2021Assignee: Qualcomm IncorporatedInventors: Hoan Huu Nguyen, Francois Ibrahim Atallah, Keith Alan Bowman, Jihoon Jeong
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Patent number: 10978139Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.Type: GrantFiled: June 4, 2019Date of Patent: April 13, 2021Assignee: Qualcomm IncorporatedInventors: Hoan Huu Nguyen, Francois Ibrahim Atallah, Keith Alan Bowman, Daniel Yingling, Jihoon Jeong, Yu Pu
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Publication number: 20200388327Abstract: A dual-mode memory is provided that includes a self-timed clock circuit for asserting a sense enable signal for a sense amplifier. In a low-bandwidth read mode, the self-timed clock circuit asserts the sense enable signal only once during a memory clock cycle. The sense amplifier then senses only a single bit from a group of multiplexed columns. In a high-bandwidth read mode, the self-timed clock circuit successively asserts the sense enable signal so that the sense amplifier successively senses bits from the multiplexed columns.Type: ApplicationFiled: June 4, 2019Publication date: December 10, 2020Inventors: Hoan Huu NGUYEN, Francois Ibrahim Atallah, Keith Alan Bowman, Daniel Yingling, Jihoon Jeong, Yu Pu
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Publication number: 20200357462Abstract: A high bandwidth register file circuit that significantly reduces the shared local read bitline RC delay to enable ultra-high performance PRFs with high port counts. In one example, the register file circuit includes read stack nfets in a multiplexer circuit instead of the memory cell causing the local read bitline RC to be independent of the number of read and write ports of the memory cell.Type: ApplicationFiled: May 8, 2019Publication date: November 12, 2020Inventors: Hoan Huu NGUYEN, Francois Ibrahim ATALLAH, Keith Alan BOWMAN, Jihoon JEONG
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Patent number: 10658029Abstract: Certain aspects of the present disclosure provide apparatus and methods for performing memory read operations. One example method generally includes precharging a plurality of memory columns during a precharging phase of a read access cycle. The method also includes sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle, and sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.Type: GrantFiled: September 21, 2018Date of Patent: May 19, 2020Assignee: QUALCOMM IncorporatedInventors: Hoan Huu Nguyen, Francois Ibrahim Atallah, Keith Alan Bowman, Hari Rao
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Patent number: 10622043Abstract: Multi-pump memory system access circuits for sequentially executing parallel memory operations in a memory system are disclosed. A memory system includes a plurality of memory bit cells in a memory array. Each memory bit cell is accessible at a corresponding memory address used by memory read and write operations. The memory system includes ports at which a memory read or a memory write operation is received from a processor in each cycle of a processor clock. To increase memory bandwidth of the memory system without increasing the number of access ports of the memory array within the memory system, a double-pump memory system access circuit double-pumps (i.e., time-multiplexes) the access ports of memory array, effectively doubling the number of ports of the memory array. The double-pump memory system access circuit performs sequential accesses to a port of a memory cell in a memory array within a processor clock period.Type: GrantFiled: September 10, 2018Date of Patent: April 14, 2020Assignee: Qualcomm IncorporatedInventors: Hoan Huu Nguyen, Jihoon Jeong, Francois Ibrahim Atallah, Keith Alan Bowman
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Publication number: 20200098422Abstract: Certain aspects of the present disclosure provide apparatus and methods for performing memory read operations. One example method generally includes precharging a plurality of memory columns during a precharging phase of a read access cycle. The method also includes sensing first data stored in a first memory cell of a first memory column of the plurality of memory columns during a memory read phase of the read access cycle, and sensing second data stored in a second memory cell of a second memory column of the plurality of memory columns during the same memory read phase of the read access cycle.Type: ApplicationFiled: September 21, 2018Publication date: March 26, 2020Inventors: Hoan Huu NGUYEN, Francois Ibrahim ATALLAH, Keith Alan BOWMAN, Hari RAO