Abstract: A power supply interface suitable to provide voltages of appropriate magnitude to a static random access memory (SRAM) device from a combination of independent sources including a main power supply, an auxiliary power supply, and a battery. The voltages from the interface are at levels consistent with the SRAM modes of operation. During limited voltage tolerance read and write access operations, main power supply voltage is provided through a low forward voltage drop switched metal oxide field effect transistor (MOSFET). Parasitic paths, potentially producible by the transistor and affecting the battery source of power, are eliminated through the use of a second, complementary MOSFET. The second MOSFET is directly responsive to a POWERGOOD signal from the main power supply, indicating both an "on" state and an appropriate voltage level of the main power supply.