Patents by Inventor Keith Best
Keith Best has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7531040Abstract: A method is disclosed for one embodiment. An amount of photoresist is deposited upon a substrate, the amount of photoresist more than necessary to coat the substrate. The substrate is spun within a bowl such that an excess amount of photoresist is propelled off of the substrate to an interior surface of the bowl. A portion of the excess amount of photoresist is recovered and treated such that the recovered portion of the excess amount of photoresist is rendered usable.Type: GrantFiled: October 2, 2003Date of Patent: May 12, 2009Assignee: ASML Holdings N.V.Inventors: Joseph Consolini, Keith Best, Cheng Gui, Alexander Friz
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Publication number: 20070196746Abstract: Embodiments of the invention provide methods and apparatuses for efficient and cost-effective imaging of alignment marks. For one embodiment, alignment mark imaging is accomplished separately from, and independent of product imaging through use of a relatively low cost, low resolution, imaging tool. For one embodiment a wafer is exposed to low-resolution light source through a reticle having a number of alignment patterns corresponding to desired alignment marks. For one embodiment, global alignment marks are imaged on a backside of a wafer. Various embodiments of the invention obviate the need for a highly accurate stage and a high-resolution imaging device, and therefore reduce processing costs and processing time.Type: ApplicationFiled: April 11, 2007Publication date: August 23, 2007Inventors: Joseph Consolini, Keith Best, Cheng Gui, Alexander Friz
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Patent number: 7256865Abstract: Embodiments of the invention provide methods and apparatuses for efficient and cost-effective imaging of alignment marks. For one embodiment, alignment mark imaging is accomplished separately from, and independent of product imaging through use of a relatively low cost, low resolution, imaging tool. For one embodiment a wafer is exposed to low-resolution light source through a reticle having a number of alignment patterns corresponding to desired alignment marks. For one embodiment, global alignment marks are imaged on a backside of a wafer. Various embodiments of the invention obviate the need for a highly accurate stage and a high-resolution imaging device, and therefore reduce processing costs and processing time.Type: GrantFiled: October 24, 2003Date of Patent: August 14, 2007Assignee: ASML Holding N.V.Inventors: Joseph Consolini, Keith Best, Cheng Gui, Alexander Friz
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Publication number: 20070037077Abstract: A second substrate, e.g. a III/V compound semiconductor, is placed on a first substrate, e.g. a wafer, in the vicinity of placement marks on the first substrate. The second substrate is exposed to patterned radiation, e.g. for the manufacture of integrated circuits.Type: ApplicationFiled: August 3, 2005Publication date: February 15, 2007Applicant: ASML NETHERLANDS B.V.Inventors: Keith Best, Johannes Maria Krikhaar, Rudy Maria Pellens
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Publication number: 20060292463Abstract: The present invention relates to a device manufacturing method wherein a plurality of front side marks are manufactured on the front side of the substrate. These marks are used to locally align the substrate when exposing. After certain processing steps, the positions of the front side marks are measured and compared with respect to their original positions. The measured position changes of the front side marks, i.e. their behaviour, can then be analyzed. The original positions and actual positions are defined with respect to a nominal grid which is defined using global alignment marks which are positioned at the back side of the substrate. Because the global alignment marks are positioned at the back side, they are not affected by any processing step.Type: ApplicationFiled: June 28, 2005Publication date: December 28, 2006Applicant: ASML Netherlands B.V.Inventors: Keith Best, Joseph Consolini, Alexander Friz
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Publication number: 20060172507Abstract: A substrate bonding system has a first and a second substrate table for holding a first substrate and a second substrate, respectively, and a controller. The first substrate includes a first device having first contact pads and the second substrate a second device having second contact pads. The wafer bonding system is arranged to bond the first and second device in such a way that a circuit may be formed by the first and second device. The first and second substrate tables each include a position sensor arranged to measure an optical signal generated on an alignment marker of the first and second substrate, respectively. The first and second substrate tables include a first and second actuator respectively that is arranged to alter a position and orientation of the respective substrate table.Type: ApplicationFiled: December 27, 2005Publication date: August 3, 2006Applicant: ASML Netherlands B. V.Inventors: Keith Best, Geoffrey Phillipps, Franciscus Casper Bijnen, Enno Den Brink, Henricus Maria Van Buel, Joseph Consolini, Peter Berge
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Publication number: 20060141744Abstract: The invention provides a method of forming a bonded substrate that includes providing a first substrate having a first substrate shape and at least one first alignment mark positioned at a first surface side. A second substrate is providing having a second substrate shape. The second substrate is oriented relative to the first substrate in a predetermined orientation. The second substrate is bonded to the first surface side of the first substrate to render the bonded substrate, such that the bonded second substrate does not cover the at least one first alignment mark.Type: ApplicationFiled: December 27, 2004Publication date: June 29, 2006Applicant: ASML NETHERLANDS B.V.Inventors: Keith Best, Joseph Consolini
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Publication number: 20060138681Abstract: Provided are substrates, e.g. semiconductor wafers, whereby the front side of the substrate and the back side of the substrate differ in surface roughness. Also provided are lithography processes using the substrates.Type: ApplicationFiled: February 11, 2005Publication date: June 29, 2006Applicant: ASML NETHERLANDS B.V.Inventors: Keith Best, Joseph Consolini, Alexander Friz, Rodney Chisholm
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Publication number: 20060141743Abstract: A substrate bonding system has a first and a second substrate table for holding a first substrate and a second substrate, respectively, and a controller. The first substrate includes a first device having first contact pads and the second substrate a second device having second contact pads. The wafer bonding system is arranged to bond the first and second device in such a way that a circuit may be formed by the first and second device. The first and second substrate tables each include a position sensor arranged to measure an optical signal generated on an alignment marker of the first and second substrate, respectively. The first and second substrate tables include a first and second actuator respectively that is arranged to alter a position and orientation of the respective substrate table.Type: ApplicationFiled: December 27, 2004Publication date: June 29, 2006Applicant: ASML NETHERLANDS B.V.Inventors: Keith Best, Joseph Consolini
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Publication number: 20060141738Abstract: In a method for measuring the bonding quality of bonded substrates, such as bonded SOI wafers, a plurality of marks are created at a first side of a top substrate after, or before, the bonding of the top substrate onto a bottom substrate. Then, the positions of the plurality of marks are measured using a metrology tool. Next, for each of the marks, a difference between a measured position and an expected position is calculated. These differences can be used to determine delamination between the top substrate and the bottom substrate. By displaying a vector field representing the differences, and by not showing vectors that exceed a certain threshold, the delamination areas can be made visible.Type: ApplicationFiled: December 27, 2004Publication date: June 29, 2006Applicant: ASML NETHERLANDS B.V.Inventors: Keith Best, Joseph Consolini, Alexander Friz
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Publication number: 20060035159Abstract: In a method according to one embodiment, a first and second set of alignment marks are etched into a first side of the substrate. The first set of alignment marks are at location(s) such that they will appear in the object windows of front-to-backside alignment optics of a first lithographic apparatus, and the location(s) of the second set of alignment marks are selected according to an arrangement of alignment apparatus in another lithographic apparatus. The substrate is turned over, aligned using the first set of alignment marks and front-to-backside alignment optics and third and fourth set of alignment marks are etched into the substrate, directly opposite the second and first sets of alignment marks, respectively.Type: ApplicationFiled: August 10, 2004Publication date: February 16, 2006Applicant: ASML NETHERLANDS B.V.Inventors: Keith Best, Joseph Consolini, Alexander Friz
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Publication number: 20050146721Abstract: In a method of measurement according to one embodiment of the invention, a relative position of a temporary alignment mark on one side of a substrate and an alignment mark on the other side of the substrate is determined, and the temporary alignment mark is removed. Before removal of the temporary alignment mark, a relative position of that mark and another mark on the same side of the substrate may be determined. The temporary alignment mark may be formed in, e.g., an oxide layer.Type: ApplicationFiled: December 24, 2003Publication date: July 7, 2005Applicant: ASML NETHERLANDS B.V.Inventors: Joseph Consolini, Keith Best, Alexander Friz
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Publication number: 20050140951Abstract: A lithographic projection apparatus is provided with an optical system built into the wafer table for producing an image of a wafer mark that is provided on the back side of the wafer. The image is located at the plane of the front side of the wafer and can be viewed by an alignment system from the front side of the wafer. Simultaneous alignment between marks on the back and front of the wafer and a mask can be performed using a pre-existing alignment system.Type: ApplicationFiled: September 14, 2004Publication date: June 30, 2005Applicant: ASML NETHERLANDS B.V.Inventors: Henricus Wilhelmus Van Buel, Keith Best, Joseph Consolini, Joeri Lof, Edwin Shafer
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Publication number: 20050089762Abstract: Embodiments of the invention provide methods and apparatuses for efficient and cost-effective imaging of alignment marks. For one embodiment, alignment mark imaging is accomplished separately from, and independent of product imaging through use of a relatively low cost, low resolution, imaging tool. For one embodiment a wafer is exposed to low-resolution light source through a reticle having a number of alignment patterns corresponding to desired alignment marks. For one embodiment, global alignment marks are imaged on a backside of a wafer. Various embodiments of the invention obviate the need for a highly accurate stage and a high-resolution imaging device, and therefore reduce processing costs and processing time.Type: ApplicationFiled: October 24, 2003Publication date: April 28, 2005Inventors: Joseph Consolini, Keith Best, Cheng Gui, Alexander Friz
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Publication number: 20050072733Abstract: A method is disclosed for one embodiment. An amount of photoresist is deposited upon a substrate, the amount of photoresist more than necessary to coat the substrate. The substrate is spun within a bowl such that an excess amount of photoresist is propelled off of the substrate to an interior surface of the bowl. A portion of the excess amount of photoresist is recovered and treated such that the recovered portion of the excess amount of photoresist is rendered usable.Type: ApplicationFiled: October 2, 2003Publication date: April 7, 2005Inventors: Joseph Consolini, Keith Best, Cheng Gui, Alexander Friz
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Publication number: 20050073669Abstract: A device manufacturing method capable of imaging structures on both sides of a substrate, is presented herein. One embodiment of the present invention comprises a device manufacturing method that etches reversed alignment markers on a first side of a substrate to a depth of 10 ?m, the substrate is flipped over, and bonded to a carrier wafer and then lapped or ground to a thickness of 10 ?m to reveal the reversed alignment markers as normal alignment markers. The reversed alignment markers may comprise normal alignment patterns overlaid with mirror imaged alignment patterns.Type: ApplicationFiled: November 24, 2004Publication date: April 7, 2005Applicant: ASML NETHERLANDS B.V.Inventors: Keith Best, Joseph Consolini, Shyam Shinde