Abstract: An alternate multi-thread pipeline structure and method are provided. A deep pipeline is provided in which two threads of two separate pipeline stages are alternatively presented to the various logic and latch circuits for execution. The execution and latching of the threads alternates from one thread to the other within a single clock cycle. Thus, each thread is executed once per clock cycle and two threads are executed in a single clock cycle.

Abstract: Embodiments of systems, methods, and computer program products may facilitate translation of machine code associated with a first processor for execution on a second processor. Machine code associated with a first processor may be translated into a translated program that includes one or more translation instructions for execution on the second processor. The one or more translation instructions are used exclusively to translate machine code that is associated with a processor other than the second processor. The translated program may be stored in a storage medium where it may be executed using the second processor. Each translation instruction that involves access of the storage medium may be dispatched to one or more translation load-store units that are dedicated exclusively to processing the translation instructions.

Abstract: An alternate multi-thread pipeline structure and method are provided. A deep pipeline is provided in which two threads of two separate pipeline stages are alternatively presented to the various logic and latch circuits for execution. The execution and latching of the threads alternates from one thread to the other within a single clock cycle. Thus, each thread is executed once per clock cycle and two threads are executed in a single clock cycle.

Abstract: Embodiments of systems, methods, and computer program products may facilitate translation of machine code associated with a first processor for execution on a second processor. Machine code associated with a first processor may be translated into a translated program that includes one or more translation instructions for execution on the second processor. The one or more translation instructions are used exclusively to translate machine code that is associated with a processor other than the second processor. The translated program may be stored in a storage medium where it may be executed using the second processor. Each translation instruction that involves access of the storage medium may be dispatched to one or more translation load-store units that are dedicated exclusively to processing the translation instructions.