Patents by Inventor Keith Chugg

Keith Chugg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080098286
    Abstract: Systems and techniques for transmitting an Irregular Systematic with Serially Concatenated Parity (Ir-S-SCP) are described. The techniques include generating an outer code comprising a plurality of bits using systematic bits as input, repeating the plurality of bits of the outer code a pre-determined number of times to generate at least a first set of repeated bits and a second set of repeated bits, serializing the generated sets of repeated bits, wherein each generated set is serialized in parallel with another generated set, interleaving the generated sets of repeated bits, generating an inner code, the inner code generated in part based on the interleaved sets, puncturing the inner code to output parity bits, wherein the puncturing is non-uniform and the puncturing is based at least in part on an incremental redundancy scheme, and transmitting the parity bits, wherein the transmitted parity bits and the systematic bits comprise the Ir-S-SCP code.
    Type: Application
    Filed: October 19, 2007
    Publication date: April 24, 2008
    Inventors: Keith Chugg, Jordan Melzer
  • Publication number: 20070011566
    Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bits in accordance with a parity check matrix (H-matrix) to generate a sequence of encoded bits, wherein the H-matrix is capable of being partitioned into a first matrix and a second matrix, the first matrix being a dual-diagonal matrix, the second matrix comprising one or more vertically stacked sub-matrices, each sub-matrix consisting of a plurality of columns, each column having a column weight of no more than 1, wherein the second matrix is capable of being expressed as a product of a parity check matrix, an interleaver permutation matrix, and a repeat block matrix, and the interleaver permutation matrix satisfies a clash-free interleaver constraint, and outputting the sequence of encoded bits.
    Type: Application
    Filed: April 14, 2006
    Publication date: January 11, 2007
    Applicant: TrellisWare Technologies, Inc.
    Inventors: Paul Gray, Keith Chugg
  • Publication number: 20060031737
    Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits, processing the outer encoded bits using an interleaver and a single parity check (SPC) module to produce intermediate bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, processing the inner encoded bits using a puncture module to produce punctured bits, and combining the data bits and the punctured bits to produce encoded outputs. Methods, apparatuses, and systems are also presented for performing data decoding based on soft channel metrics derived from a channel using various iterative techniques.
    Type: Application
    Filed: August 12, 2005
    Publication date: February 9, 2006
    Applicant: TrellisWare Technologies, Inc.
    Inventors: Keith Chugg, Paul Gray
  • Publication number: 20050216819
    Abstract: The present invention relates to methods, apparatuses, and systems for performing data encoding involving encoding data bits according to an outer convolutional code to produce outer encoded bits processing the outer encoded bits using an interleaver and a logical unit to produce intermediate bits, wherein the logical unit receives a first number of input bits and produces a second number of corresponding output bits, the second number being less than the first number, and wherein the logical unit takes each of the first number of input bits into account in producing the second number of output bits, encoding the intermediate bits according to an inner convolutional code to produce inner encoded bits, wherein the inner convolutional code is characterized by at least two states, and combining the data bits and the inner encoded bits to produce encoded outputs.
    Type: Application
    Filed: February 16, 2005
    Publication date: September 29, 2005
    Applicant: TrellisWare Technologies, Inc.
    Inventors: Keith Chugg, Paul Gray, Georgios Dimou, Phunsak Thiennviboon