Abstract: A phototherapy system can provide functions such as user account management, skin type evaluation, treatment parameter determinations and adjustments, treatment blocking or warnings for some hazard prevention, treatment education and guidance, session records access, treatment regime determination, scheduling, and converting treatment parameter determinations into kiosk controls. The phototherapy system functions can be performed based on user input, records of user data, guidelines and algorithms for treatment parameter selection, direct measurements, etc. These data sources can be accessed or implemented though one or more of: a phototherapy kiosk, a personal computing device, a server system, a third-party system, or any combination thereof. An interactive user interface can be used though any of these devices to facilitate user control and user feedback for the phototherapy system.

Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Abstract: Techniques are disclosed relating to electromigration control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor operating conditions, implement control for one or more electromigration loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid electromigration issues, potentially with reduced impact on processor performance relative to traditional techniques.

Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.

Abstract: Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supp1 voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.

Abstract: Techniques are disclosed relating to thermal control implemented by a power management unit. In some embodiments, the power management unit itself is configured to monitor thermal conditions, implement control for one or more thermal loops, and send reduction alerts, via an inter-chip interconnect, to the processor circuitry it powers. In some embodiments, the power management unit implements both thermal and electromigration control loops. Disclosed techniques may advantageously reduce or avoid thermal issues, potentially with reduced impact on processor performance relative to traditional techniques.

Abstract: A temperature control apparatus is disclosed. An integrated circuit (IC) includes a plurality of temperature sensors, a first thermal control loop, and a second thermal control loop. The first thermal control loop is configured to control temperature of the IC by reducing a frequency of a clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a first temperature threshold. The second thermal control loop is configured to control temperature of the IC by dithering the clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a second temperature threshold that is greater than the first temperature threshold.

Abstract: A device implementing adaptive memory performance control by thread group may include a memory and at least one processor. The at least one processor may be configured to execute a group of threads on one or more cores. The at least one processor may be configured to monitor a plurality of metrics corresponding to the group of threads executing on one or more cores. The metrics may include, for example, a core stall ratio and/or a power metric. The at least one processor may be configured to determine, based at least in part on the plurality of metrics, a memory bandwidth constraint with respect to the group of threads executing on the one or more cores. The at least one processor may be configured to, in response to determining the memory bandwidth constraint, increase a memory performance corresponding to the group of threads executing on the one or more cores.

Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supply voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.

Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Abstract: Replaceable contact pads of end effectors are provided. The contact pads support substrates in electronic device manufacturing. The contact pad includes a contact pad head having a contact surface configured to contact a substrate, a shaft coupled to the contact pad head, the shaft including a shaft indent formed between an underside of the contact pad head and a shaft end, and a circular securing member received around the shaft and seated in the shaft indent and configured to secure the contact pad to the end effector body. End effectors including replaceable contact pads and maintenance methods are described, as are additional aspects.

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Different sets of power delivery trigger circuits may be coupled to the integrated circuit by wiring or serial communication interfaces. Power reduction responses may be implemented at faster rates utilizing the wired power delivery trigger circuits while slower power reduction response can be implemented utilizing serially connected power delivery trigger circuits. The threshold for power reduction response by wired power delivery trigger circuits may also be closer to a functional failure point of the integrated circuit in order to provide fast response to avoid failure of the integrated circuit.

Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level suppl voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.

Abstract: A temperature control apparatus is disclosed. An integrated circuit (IC) includes a plurality of temperature sensors, a first thermal control loop, and a second thermal control loop. The first thermal control loop is configured to control temperature of the IC by reducing a frequency of a clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a first temperature threshold. The second thermal control loop is configured to control temperature of the IC by dithering the clock signal provided to the IC in response to a temperature at one of the plurality of temperature sensors reaching a second temperature threshold that is greater than the first temperature threshold.

Abstract: In one embodiment, a system includes power management control that controls a duty cycle of a processor to manage power. The duty cycle may be the amount of time that the processor is powered on as a percentage of the total time. By frequently powering up and powering down the processor during a period of time, the power consumption of the processor may be controlled while providing the perception that the processor is continuously available. For example, the processor may be a graphics processing unit (GPU), and the period of time over which the duty cycle is managed may be a frame to be displayed on the display screen viewed by a user of the system.